Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 351
PIC24FJ128GC010 FAMILY
REGISTER 26-2: ADCON2: A/D CONTROL REGISTER 2
R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1
PVCFG1 PVCFG0 —NVCFG0—BUFORG r r
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
r r — — — — REFPUMP
(1)
r
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 PVCFG<1:0>: Converter Voltage Reference Configuration for ADREF+ bits
10 = BGBUF1 Internal Reference
(2)
01 =External VREF+
00 =A
VDD
bit 13 Unimplemented: Read as ‘0’
bit 12 NVCFG0: Converter Voltage Reference Configuration for ADREF- bit
1 =External VREF-
0 =A
VSS
bit 11 Unimplemented: Read as ‘0’
bit 10 BUFORG: ADRES Result Buffer Organization Control bit
1 = Result buffer is organized as an indexed buffer; ADTBLn conversion result is stored in ADRESn
(where n is the same number between 0-31)
0 = Result buffer is organized as a 32 result deep FIFO like buffer; results get stored in the sequential
order that they are generated
bit 9-8 Reserved: Always write ‘11’ to these bits for normal A/D operation
bit 7-6 Reserved: Always write ‘00’ to these bits for normal A/D operation
bit 5-2 Unimplemented: Read as ‘0’
bit 1 REFPUMP: A/D Reference Charge Pump Control bit
(1)
1 = Reference charge pump is enabled, to optimize internal operation with small references < (0.65 * AVDD)
0 = Reference charge pump is disabled
bit 0 Reserved: Always write ‘0’ to this bit for normal A/D operation
Note 1: Never set the REFPUMP bit unless the magnitude of the A/D reference (ex: AVREF+ – AVREF-) is less than
(0.65 * AV
DD).
2: In order to use the BGBUF1 internal reference for the A/D, firmware must also configure and enable the
buffer through the BUFCON1.