Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 349
PIC24FJ128GC010 FAMILY
FIGURE 26-1: 12-BIT PIPELINE A/D CONVERTER BLOCK DIAGRAM
V REF +
AN48
(1)
AN49
(1)
AN16
(1)
AN47
(1)
AN14
AN15
AN0
AN1
AN2
V REF -
Sample Control
AV SS
AV DD
ADCON1
ADCON2
ADCON3
ACCONL
ACCONH
ADCHITL
Input MUX Control
Internal Data Bus
16
V
R+VR-
VINH
VINL
VR+
V
R-
VR Select
V BG
ADCHITH
Note 1: Not all external analog inputs are implemented on all devices. See Table 1-3 for a list of implemented channels by
pin count.
CTMU
V
BAT
AV SS
AV DD
ADSTATH
V BG /2
BGBUF1
DMA Data
16
ADSTATL
BGBUF0
Tem p
OPA1O
OPA2O
Input Channel MUX
ADLnCONH
ADLnCONL
ADLnSTAT
ADLnPTR
ADTBLn
ADTnH1H
ADTnH1L
ADLnMSEL3
ADLnMSEL2
ADLnMSEL1
ADLnMSEL0
(n = 0-3)
Threshold Detect
and Compare Data
S/H
Bus
Control Logic
and
Sample List
Sequencing
Data Formatting
12-Bit A/D
(Result Buffer)
ADRES31:
ADRES0
Conversion Logic