Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 347
PIC24FJ128GC010 FAMILY
26.0 12-BIT HIGH-SPEED, PIPELINE
A/D CONVERTER
The 12-Bit Pipeline A/D Converter has the following
key features:
• Conversion Speeds of up to 10 Msps
• Up to 50 Analog Single-Ended Input Channels or
up to 15 Unique Differential Input Channel Pairs
• 12-Bit Conversion Resolution
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Extended Automated and Fully Programmable
Sampling Sequences from up to Four Different Lists
• Conversion Result Accumulation
• Selectable Conversion Trigger Source
• Internal 32-Word, Configurable Conversion Result
Buffer
• Eight Options for Results Alignment
• Configurable Interrupt Generation
• Operation During CPU Sleep and Idle modes
The A/D Converter module is a pipelined 12-bit A/D
Converter, capable of sampling up to once per A/D
clock cycle. Its operation is enhanced with a wide range
of automatic sampling options, tighter integration with
other analog modules, result accumulation across
many samples and a configurable results buffer.
A simplified block diagram for the module is shown in
Figure 26-1.
26.1 Basic Operation
To perform a standard A/D conversion:
1. Configure the module:
a) Configure port pins as analog inputs by setting
the appropriate bits in the ANSx registers (see
Section 11.2 “Configuring Analog Port
Pins (ANSx)” for more information).
b) Configure “global” ADCON1, ADCON2 and
ADCON3 control settings, but do not set the
ADON bit until all global settings are
configured:
• Configure A/D clock source/rate
• Select A/D reference sources
• Configure data formatting
• Configure other settings
c) Enable the A/D module by setting the
ADON bit (ADCON1<15>).
d) Wait until the ADREADY bit (ADSTATH<1>)
becomes set, indicating the module is finished
with internal calibration and initialization.
e) Configure Sample List 0 settings, controlled
by the ADL0CONH and ADL0CONL regis-
ters, but do not enable the sample list yet
(SLEN):
• Select the desired sample list interrupt
generation settings
• Select a Data Write mode (ex: write all
results to buffer)
• Configure analog sampling time
(SAMC<4:0>)
• Select a trigger source
• Specify how many entries are in the
sample list (SLSIZE<4:0>)
• Configure other Sample List 0 specific
settings
f) Initialize the ADTBL0 register (and higher if
SLSIZEx > 0) to select the analog channel(s)
to be included in Sample List 0.
g) Configure and enable A/D interrupts (if
desired):
• Clear the AD1IF and SL0IF bits
• Select an interrupt priority
• Enable AD1IE
h) Enable Sample List 0 by setting the SLEN
bit (in ADL0CONL<15>).
i) Generate a trigger event for Sample List 0
(as configured in Step e).
j) Wait for the SL0IF or top level AD1IF inter-
rupt flag to assert, indicating that the A/D
result(s) are now ready.
k) Read the respective result(s) from the appro-
priate ADRESn register(s) (as configured
based on the BUFORG setting).
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the Pipe-
line A/D Converter, refer to the “PIC24F
Family Reference Manual”, “12-Bit,
High-Speed Pipeline A/D Converter”
(DS30686).