Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 327
PIC24FJ128GC010 FAMILY
REGISTER 23-2: RTCPWC: RTCC POWER CONTROL REGISTER
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWCEN PWCPOL PWCPRE PWSPRE RTCLK1
(2)
RTCLK0
(2)
RTCOUT1 RTCOUT0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWCEN: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
bit 14 PWCPOL: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
bit 13 PWCPRE: Power Control/Stability Prescaler bit
1 = PWC stability window clock is divide-by-2 of source RTCC clock
0 = PWC stability window clock is divide-by-1 of source RTCC clock
bit 12 PWSPRE: Power Control Sample Prescaler bit
1 = PWC sample window clock is divide-by-2 of source RTCC clock
0 = PWC sample window clock is divide-by-1 of source RTCC clock
bit 11-10 RTCLK<1:0>: RTCC Clock Source Select bits
(2)
11 = External power line (60 Hz)
10 = External power line source (50 Hz)
01 = Internal LPRC Oscillator
00 = External Secondary Oscillator (SOSC)
bit 9-8 RTCOUT<1:0>: RTCC Output Source Select bits
11 = Power control
10 = RTCC clock
01 = RTCC seconds clock
00 = RTCC alarm pulse
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The RTCPWC register is only affected by a POR.
2: When a new value is written to these register bits, the lower half of the MINSEC register should also be
written to properly reset the clock prescalers in the RTCC.