Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 306  2012-2013 Microchip Technology Inc.
bit 1-0 IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = Reserved
01 = Interrupt is generated at the end of a read/write cycle
00 = No interrupt is generated
REGISTER 21-1: PMCON1: EPMP CONTROL REGISTER 1 (CONTINUED)
REGISTER 21-2: PMCON2: EPMP CONTROL REGISTER 2
R-0, HSC U-0 R/C-0, HS R/C-0, HS U-0 U-0 U-0 U-0
BUSY — ERROR TIMEOUT — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RADDR23
(1)
RADDR22
(1)
RADDR21
(1)
RADDR20
(1)
RADDR19
(1)
RADDR18
(1)
RADDR17
(1)
RADDR16
(1)
bit 7 bit 0
Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
C = Clearable bit
bit 15 BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14 Unimplemented: Read as ‘0’
bit 13 ERROR: Error bit
1 = Transaction error (illegal transaction was requested)
0 = Transaction completed successfully
bit 12 TIMEOUT: Time-out bit
1 = Transaction timed out
0 = Transaction completed successfully
bit 11-8 Unimplemented: Read as ‘0’
bit 7-0 RADDR<23:16>: Parallel Master Port Reserved Address Space bits
(1)
Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh.