Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 303
PIC24FJ128GC010 FAMILY
21.0 ENHANCED PARALLEL
MASTER PORT (EPMP)
The Enhanced Parallel Master Port (EPMP) module pro-
vides a parallel, 4-bit (Master mode only), 8-bit (Master
and Slave modes) or 16-bit (Master mode only) data bus
interface to communicate with off-chip modules, such as
memories, FIFOs, LCD controllers and other microcon-
trollers. This module can serve as either the master or
the slave on the communication bus.
For EPMP Master modes, all external addresses are
mapped into the internal Extended Data Space (EDS).
This is done by allocating a region of the EDS for each
Chip Select (CS) and then assigning each Chip Select
to a particular external resource, such as a memory or
external controller. This region should not be assigned
to another device resource, such as RAM or SFRs. To
perform a write or read on an external resource, the
CPU simply performs a write or read within the address
range assigned for the EPMP.
Key features of the EPMP module are:
• Extended Data Space (EDS) Interface Allows
Direct Access from the CPU
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select Lines
• Up to 2 Acknowledgment Lines
(one per Chip Select)
• 4-Bit, 8-Bit or 16-Bit Wide Data Bus
• Programmable Strobe Options (per Chip Select):
- Individual Read and Write Strobes; or
- Read/Write
Strobe with Enable Strobe
• Programmable Address/Data Multiplexing
• Programmable Address Wait States
• Programmable Data Wait States (per Chip Select)
• Programmable Polarity on Control Signals
(per Chip Select)
• Legacy Parallel Slave Port (PSP) Support
• Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
21.1 Specific Package Variations
While all PIC24FJ128GC010 family devices implement
the EPMP, I/O pin constraints place some limits on
16-Bit Master mode operations in some package types.
This is reflected in the number of dedicated Chip Select
pins implemented and the number of dedicated
address lines that are available. The differences are
summarized in Table 21-1. All available EPMP pin
functions are summarized in Tabl e 2 1-2 .
For 64-pin devices, the dedicated Chip Select pins
(PMCS1 and PMCS2) are not implemented. In addi-
tion, only 16 address lines (PMA<15:0>) are available.
If required, PMA14 and PMA15 can be remapped to
function as PMCS1 and PMCS2, respectively.
The memory space addressable by the device
depends on the number of address lines available, as
well as the number of Chip Select signals required for
the application. Devices with lower pin counts are more
affected by Chip Select requirements, as these take
away address lines. Table 21-1 shows the maximum
addressable range for each pin count.
TABLE 21-1: EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Enhanced Parallel Master Port
(EPMP)” (DS39730). The information in
this data sheet supersedes the information
in the FRM.
Device
Dedicated Chip Select
Address
Lines
Address Range (bytes)
CS1 CS2 No CS 1 CS 2 CS
PIC24FJXXXGC006 (64-pin) — — 16 64K 32K 16K
PIC24FJXXXGC010
(100/121-pin)
X X 23 16M