Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 302  2012-2013 Microchip Technology Inc.
REGISTER 20-3: MDCAR: DATA SIGNAL MODULATOR CARRIER CONTROL REGISTER
R/W-x R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x
CHODIS CHPOL CHSYNC — CH3
(1)
CH2
(1)
CH1
(1)
CH0
(1)
bit 15 bit 8
R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x
CLODIS CLPOL CLSYNC —CL3
(1)
CL2
(1)
CL1
(1)
CL0
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHODIS: DSM High Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by CH<3:0>) is disabled
0 = Output signal driving the peripheral output pin is enabled
bit 14 CHPOL: DSM High Carrier Polarity Select bit
1 = Selected high carrier signal is inverted
0 = Selected high carrier signal is not inverted
bit 13 CHSYNC: DSM High Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier
0 = Modulator output is not synchronized to the high time carrier signal
(1)
bit 12 Unimplemented: Read as ‘0’
bit 11-8 CH<3:0>: DSM Data High Carrier Selection bits
(1)
1111
. . . = Reserved
1011
1010 = Output Compare/PWM Module 7 output
1001 = Output Compare/PWM Module 6 output
1000 = Output Compare/PWM Module 5 output
0111 = Output Compare/PWM Module 4 output
0110 = Output Compare/PWM Module 3 output
0101 = Output Compare/PWM Module 2 output
0100 = Output Compare/PWM Module 1 output
0011 = Reference clock (REFO) output
0010 = Input on MDCIN2 pin
0001 = Input on MDCIN1 pin
0000 = V
SS
bit 7 CLODIS: DSM Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by CL<3:0>) is disabled
0 = Output signal driving the peripheral output pin is enabled
bit 6 CLPOL: DSM Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
bit 5 CLSYNC: DSM Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier
0 = Modulator output is not synchronized to the low time carrier signal
(1)
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CL<3:0>: DSM Data Low Carrier Selection bits
(1)
Bit settings are identical to those for CH<3:0>.
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.