Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 289
PIC24FJ128GC010 FAMILY
REGISTER 19-12: U1CNFG1: USB CONFIGURATION REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
UTEYE UOEMON
(1)
— USBSIDL — — PPB1 PPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test is enabled
0 = Eye pattern test is disabled
bit 6 UOEMON: USB OE
Monitor Enable bit
(1)
1 =OE signal is active; it indicates intervals during which the D+/D- lines are driving
0 =OE
signal is inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 USBSIDL: USB OTG Stop in Idle Mode bit
1 = Discontinues module operation when the device enters Idle mode
0 = Continues module operation in Idle mode
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd Ping-Pong Buffers are enabled for Endpoints 1 to 15
10 = Even/Odd Ping-Pong Buffers are enabled for all endpoints
01 = Even/Odd Ping-Pong Buffers are enabled for OUT Endpoint 0
00 = Even/Odd Ping-Pong Buffers are disabled
Note 1: This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set.