Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 24  2012-2013 Microchip Technology Inc.
OA1NA 12 21 H2 I ANA Op Amp 1 Negative (inverting) Inputs.
OA1NB 53 82 B8 I ANA
OA1NC — 8 E2 I ANA
OA1ND 6 12 F2 I ANA
OA1NE 5 11 F4 I ANA
OA1OUT 11 20 H1 O — Op Amp 1 (analog) Output (digital output in Comparator
mode).
OA1PA 8 14 F3 I ANA Op Amp 1 Positive (non-inverting) Inputs.
OA1PB 4 10 E3 I ANA
OA1PC 54 83 D7 I ANA
OA1PD 17 26 L1 I ANA
OA1PE 52 81 C8 I ANA
OA2NA 46 72 D9 I ANA Op Amp 2 Negative (inverting) Inputs.
OA2NB 50 77 A10 I ANA
OA2NC 14 23 J2 I ANA
OA2ND 31 49 L10 I ANA
OA2NE 29 43 K7 I ANA
OA2OUT 13 22 J1 O — Op Amp 2 (analog) Output (digital output in Comparator
mode).
OA2PA 45 71 C11 I ANA Op Amp 2 Positive (non-inverting) Inputs.
OA2PB 15 24 K1 I ANA
OA2PC 32 50 L11 I ANA
OA2PD 28 42 L7 I ANA
OA2PE 51 78 B9 I ANA
OSCI 39 63 F9 I ANA Main Oscillator Input Connection.
OSCO 40 64 F11 O — Main Oscillator Output Connection.
PGEC1 15 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming
Clock.
PGEC2 17 26 L1 I/O ST
PGEC3 11 20 H1 I/O ST
PGED1 16 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data.
PGED2 18 27 J3 I/O ST
PGED3 12 21 H2 I/O ST
PMA0 30 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1 29 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2 8 14 F3 O — Parallel Master Port Address (bits<22:2>).
PMA3 6 12 F2 O —
PMA4 5 11 F4 O —
PMA5 4 10 E3 O —
PMA6 16 29 K3 O —
PMA7 14 28 L2 O —
TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O
Input
Buffer
Description
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer