Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 221
PIC24FJ128GC010 FAMILY
bit 3 T32: 32-Bit Timer Mode Select bit
(3)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timerx Clock Source Select bit
(2)
1 = Timer source is selected by TIECS<1:0>
0 = Internal clock (F
OSC/2)
bit 0 Unimplemented: Read as ‘0’
REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
(1)
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2: If TCS = 1 and TIECS<1:0> = x1, the selected external timer input (TMRCK or TxCK) must be configured
to an available RPn/RPIn pin. For more information, see Section 11.4 “Peripheral Pin Select (PPS)”.
3: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or
T5CON control bits do not affect 32-bit timer operation.