Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 220  2012-2013 Microchip Technology Inc.
REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER
(1)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
TON —TSIDL— — —TIECS1
(2)
TIECS0
(2)
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS1 TCKPS0 T32
(3)
—TCS
(2)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timerx On bit
When TxCON<3> =
1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON<3> =
0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 TIECS<1:0>: Timerx Extended Clock Source Select bits (selected when TCS = 1)
(2)
When TCS = 1:
11 = Generic Timer (TMRCK) External Input
10 = LPRC Oscillator
01 = TxCK External Clock Input
00 =SOSC
When TCS =
0:
These bits are ignored; timer is clocked from internal system clock (F
OSC/2).
bit 7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS =
1:
This bit is ignored.
When TCS =
0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 =1:256
10 =1:64
01 =1:8
00 =1:1
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2: If TCS = 1 and TIECS<1:0> = x1, the selected external timer input (TMRCK or TxCK) must be configured
to an available RPn/RPIn pin. For more information, see Section 11.4 “Peripheral Pin Select (PPS)”.
3: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or
T5CON control bits do not affect 32-bit timer operation.