Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 219
PIC24FJ128GC010 FAMILY
FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
T2CK
PR2 (PR4)
Set T2IF (T4IF)
Equal
Comparator
Reset
Q
QD
CK
TGATE
1
0
(T4CK)
Sync
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
TMR2 (TMR4)
TCY
TCS
(1)
TGATE
(1)
SOSC Input
LPRC Input
TIECS<1:0>
TMRCK
Gate
Sync
TON
TCKPS<1:0>
2
PR3 (PR5)
Set T3IF (T5IF)
Equal
Comparator
Reset
TGATE
1
0
A/D Event Trigger
(2)
Prescaler
1, 8, 64, 256
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
2: The A/D Event Trigger is available only on Timer3.
T3CK
(T5CK)
T
CY
TCS
(1)
TGATE
(1)
SOSC Input
LPRC Input
TIECS<1:0>
TMRCK
Gate
Sync
Q
QD
CK
TMR3 (TMR5)