Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 218  2012-2013 Microchip Technology Inc.
FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
Set T3IF (T5IF)
Equal
Reset
LSB MSB
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn/RPIn
pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
3: The A/D Event Trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode.
Data Bus<15:0>
TMR3HLD
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)
(1)
16
16
16
TGATE
0
1
TCKPS<1:0>
2
Sync
A/D Event Trigger
(3)
(TMR5HLD)
T2CK
(T4CK)
T
CY
TCS
(2)
TGATE
(2)
SOSC Input
LPRC Input
TIECS<1:0>
TMRCK
Prescaler
1, 8, 64, 256
Gate
Sync
Q
QD
CK
PR3 PR2
(PR5) (PR4)
TMR3
TMR2
(TMR5)
(TMR4)
Comparator