Datasheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 2 2012-2013 Microchip Technology Inc.
Universal Serial Bus Features
• USB v2.0 On-The-Go (OTG) Compliant
• USB Device mode Operation from FRC Oscillator –
No Crystal Oscillator Required
• Dual Role Capable – Can Act as Either Host or
Peripheral
• Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s)
USB Operation in Host mode
• Full-Speed USB Operation in Device mode
• Low Jitter PLL for USB
• Supports up to 32 Endpoints (16 bidirectional):
- USB module can use any RAM location on the
device as USB endpoint buffers
• On-Chip USB Transceiver with Interface for Off-Chip
USB Transceiver
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• On-Chip Pull-up and Pull-Down Resistors
Peripheral Features
• LCD Display Controller:
- Up to 59 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS); Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA Supports All Peripheral modules:
- Minimizes CPU overhead, increases data
throughput and lowers power consumption
• Nine Input Capture modules, Each with a Dedicated
16-Bit Timer
• Nine Output Compare/PWM modules, Each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Run, Sleep, Deep Sleep and V
BAT modes
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
•Two I
2
C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Four UART modules:
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA
®
- Auto-wake-up on Auto-Baud Detect (ABD)
- 4-level deep FIFO buffer
• Programmable, 32-Bit Cyclic Redundancy Check
(CRC) Generator
• Digital Signal Modulator (DSM) Provides On-Chip
FSK and PSK Modulation for a Digital Signal Stream
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Configurable Open-Drain Outputs on Digital I/O Pins
• 5.5V Tolerant Inputs on Select Pins
High-Performance CPU
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• C Compiler Optimized Instruction Set
Architecture (ISA)
• 8 MHz Internal Oscillator:
- 96 MHz PLL option for USB clocking
- Multiple clock divide options
- Run-time self-calibration capability for maintaining
better than ±0.20% accuracy
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory
Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for
Regular and eXtreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program
Memory, Typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Separate Brown-out Reset (BOR) and Deep Sleep
Brown-out Reset (DSBOR) Circuits
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers for
Reliable Operation in Standard and Deep Sleep
modes