Datasheet

PIC24FJ128GC010 FAMILY
DS30009312B-page 18  2012-2013 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ128GC010 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH
16
Program Counter
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
16
16
8
Interrupt
Controller
EDS and
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
HLVD & BOR
Precision
References
Band Gap
FRC/LPRC
Oscillators
Regulators
Voltage
VCAP
PORTA
(1)
PORTC
(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Tab l e 1- 3 for specific implementations by pin count .
2: These peripheral I/Os are only accessible through remappable pins.
PORTD
(1)
(16 I/O)
Comparators
(2)
Timers
Timer1
IC
A/D
12-Bit
OC/PWM
SPI
EPMP/PSP
1-9
(2)
ICNs
(1)
UART
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(10 I/O)
1/2
(2)
1/2
1/2/3/4
(2)
1-9
(2)
CTMU
LCD
Driver
Space
Program Memory/
DMA
Controller
Data
DMA
Data Bus
16
Ta bl e D ata
Access Control
VBAT
Pipeline
A/D

2/3 & 4/5
(2)
RTCC DSM
DACs
Op Amps
USB
OTG
BGBUF1
BGBUF2
10-Bit
16-Bit
Read AGU
Write AGU
I
2
C™
PCL
EA MUX
16-Bit ALU