Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 177
PIC24FJ128GC010 FAMILY
10.5 VBAT Mode
This mode represents the lowest power state that the
microcontroller can achieve and still resume operation.
V
BAT mode is automatically triggered when the micro-
controller’s main power supply on V
DD fails. When this
happens, the microcontroller’s on-chip power switch
connects to a backup power source, such as a battery,
supplied to the V
BAT pin. This maintains a few key
systems at an extremely low-power draw until V
DD is
restored.
The power supplied on V
BAT only runs two systems:
the RTCC and the Deep Sleep Semaphore registers
(DSGPR0 and DSGPR1). To maintain these systems
during a sudden loss of V
DD, it is essential to connect a
power source, other than V
DD or AVDD, to the VBAT pin.
When the RTCC is enabled, it continues to operate with
the same clock source (SOSC or LPRC) that was
selected prior to entering V
BAT mode. There is no pro-
vision to switch to a lower power clock source after the
mode switch.
Since the loss of V
DD is usually an unforeseen event, it
is recommended that the contents of the Deep Sleep
Semaphore registers be loaded with the data to be
retained at an early point in code execution.
10.5.1 VBAT MODE WITH NO RTCC
By disabling RTCC operation during VBAT mode,
power consumption is reduced to the lowest of all
power-saving modes. This is done by programming the
RTCBAT Configuration bit (CW4<9>) to ‘0’. In this
mode, only the Deep Sleep Semaphore registers are
maintained.
10.5.2 WAKE-UP FROM VBAT MODES
When VDD is restored to a device in VBAT mode, it auto-
matically wakes. Wake-up occurs with a POR, after
which, the device starts executing code from the Reset
vector. All SFRs, except the Deep Sleep Semaphore
registers, are reset to their POR values. IF the RTCC
was not configured to run during V
BAT mode, it will
remain disabled and RTCC will not run. Wake-up timing
is similar to that for a normal POR.
To differentiate a wake-up from V
BAT mode from other
POR states, check the VBAT status bit (RCON2<0>). If
this bit is set while the device is starting to execute the
code from the Reset vector, it indicates that there has
been an exit from V
BAT mode. The application must
clear the VBAT bit to ensure that future V
BAT wake-up
events are captured.
If a POR occurs without a power source connected to
the V
BAT pin, the VBPOR bit (RCON2<1>) is set. If this
bit is set on a POR, it indicates that a battery needs to
be connected to the VBAT pin.
In addition, if the V
BAT power source falls below the
level needed for Deep Sleep semaphore operation
while in VBAT mode (e.g., the battery has been
drained), the VBPOR bit will be set. VBPOR is also set
when the microcontroller is powered up the very first
time, even if power is supplied to V
BAT.
10.5.3 I/O PINS DURING VBAT MODES
All I/O pins switch to Input mode during VBAT mode.
The only exceptions are the SOSCI and SOSCO pins,
which maintain their states if the Secondary Oscillator
is being used as the RTCC clock source. It is the user’s
responsibility to restore the I/O pins to their proper
states, using the TRISx and LATx bits, once V
DD has
been restored.
10.5.4 SAVING CONTEXT DATA WITH THE
DSGPRx REGISTERS
As with Deep Sleep mode (i.e., without the
low-voltage/retention regulator), all SFRs are reset to
their POR values after V
DD has been restored. Only the
Deep Sleep Semaphore registers are preserved. Appli-
cations which require critical data to be saved should
save it in DSGPR0 and DSGPR1.
The POR should be enabled for the reliable operation
of the V
BAT.
Note: If the V
BAT mode is not used, it is
recommended to connect the V
BAT pin
to V
DD.