Datasheet

 2012-2013 Microchip Technology Inc. DS30009312B-page 171
PIC24FJ128GC010 FAMILY
10.0 POWER-SAVING FEATURES
The PIC24FJ128GC010 family of devices provides the
ability to manage power consumption by selectively man-
aging clocking to the CPU and the peripherals. In general,
a lower clock frequency and a reduction in the number of
circuits being clocked reduces consumed power.
PIC24FJ128GC010 family devices manage power
consumption with five strategies:
• Instruction-Based Power Reduction Modes
• Hardware-Based Power Reduction Features
• Clock Frequency Control
• Software Controlled Doze Mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
10.1 Overview of Power-Saving Modes
In addition to full-power operation, otherwise known as
Run mode, the PIC24FJ128GC010 family of devices
offers three Instruction-Based Power-Saving modes
and one Hardware-Based mode:
•Idle
• Sleep (Sleep and Low-Voltage Sleep)
• Deep Sleep (with and without retention)
•V
BAT (with and without RTCC)
All four modes can be activated by powering down dif-
ferent functional areas of the microcontroller, allowing
progressive reductions of operating and Idle power
consumption. In addition, three of the modes can be
tailored for more power reduction, at a trade-off of
some operating features. Table 1 0 - 1 lists all of the
operating modes, in order of increasing power savings.
Table 10-2 summarizes how the microcontroller exits
the different modes. Specific information is provided in
the following sections.
TABLE 10-1: OPERATING MODES FOR PIC24FJ128GC010 FAMILY DEVICES
Note: This data sheet summarizes the features of
this group of PIC24FJ devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Power-Saving Features with Deep
Sleep” (DS39727).
Mode Entry
Active Systems
Core Peripherals
Data RAM
Retention
RTCC
(1)
DSGPR0/
DSGPR1
Retention
Run (default) N/AYYYYY
Idle Instruction N Y Y Y Y
Sleep:
Sleep Instruction N S
(2)
YYY
Low-Voltage Sleep Instruction +
RETEN bit
NS
(2)
YYY
Deep Sleep:
Retention Deep
Sleep
Instruction +
DSEN bit +
RETEN bit
NNYYY
Deep Sleep Instruction +
DSEN bit
NNNYY
V
BAT:
with RTCC Hardware N N N Y Y
w/o RTCC Hardware +
RTCBAT
Config. bit
NNNNY
Note 1: If RTCC is otherwise enabled in firmware.
2: A select peripheral can operate during this mode from LPRC or some external clock.