Datasheet
PIC24FJ128GC010 FAMILY
DS30009312B-page 100 2012-2013 Microchip Technology Inc.
TABLE 7-1: RESET FLAG BIT OPERATION
REGISTER 7-2: RCON2: RESET AND SYSTEM CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 r-0 R/CO-1 R/CO-1 R/CO-1 R/CO-0
— — — r VDDBOR
(1)
VDDPOR
(1,2)
VBPOR
(1,3)
VBAT
(1)
bit 7 bit 0
Legend: CO = Clearable Only bit r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 Reserved: Maintain as ‘0’
bit 3 VDDBOR: V
DD Brown-out Reset Flag bit
(1)
1 =A VDD Brown-out Reset has occurred (set by hardware)
0 =A V
DD Brown-out Reset has not occurred
bit 2 VDDPOR: V
DD Power-on Reset Flag bit
(1,2)
1 =A VDD Power-on Reset has occurred (set by hardware)
0 =A V
DD Power-on Reset has not occurred
bit 1 VBPOR: VBAT Power-on Reset Flag bit
(1,3)
1 =A VBAT POR has occurred (no battery connected to VBAT pin or VBAT power is below Deep Sleep
semaphore retention level, set by hardware)
0 =A V
BAT POR has not occurred
bit 0 VBAT: V
BAT Flag bit
(1)
1 = A POR exit has occurred while power was applied to VBAT pin (set by hardware)
0 = A POR exit from V
BAT has not occurred
Note 1: This bit is set in hardware only; it can only be cleared in software.
2: Indicates a V
DD POR. Setting the POR bit (RCON<0>) indicates a VCORE POR.
3: This bit is set when the device is originally powered up, even if power is present on V
BAT.
Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event POR
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR
Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out CLRWDT, PWRSAV Instruction, POR
SLEEP (RCON<3>) PWRSAV #0 Instruction POR
DPSLP (RCON<10>) PWRSAV #0 Instruction while DSEN bit set POR
IDLE (RCON<2>) PWRSAV #1 Instruction POR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
Note: All Reset flag bits may be set or cleared by the user software.