PIC24FJ128GC010 FAMILY 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology Advanced Analog Features Extreme Low-Power Features • 12-Bit, up to 50-Channel, High-Speed, Pipelined Analog-to-Digital (A/D) Converter: - Conversion rates up to 10 Msps - Compatibility features for low conversion rates - Flexible operating modes with auto-accumulate, Threshold Detect and channel scan using sample lists - Conversion available during Sleep and Idle • 16-Bit Sigma
PIC24FJ128GC010 FAMILY Universal Serial Bus Features High-Performance CPU • USB v2.0 On-The-Go (OTG) Compliant • USB Device mode Operation from FRC Oscillator – No Crystal Oscillator Required • Dual Role Capable – Can Act as Either Host or Peripheral • Low-Speed (1.
PIC24FJ128GC010 FAMILY Pin Diagrams 64-Pin TQFP (10 mm x 10 mm) 49 50 51 52 53 54 55 56 57 59 58 60 61 62 64 63 RE4 RE3 RE2 RE1 RE0 RF1 RF0 VBAT VCAP RD7 RD6 RD5 RD4 RD3 RD2 RD1 64-Pin QFN (9 mm x 9 mm)(1) 48 RE5 RE6 1 RE7 RG6 RG7 RG8 MCLR 3 46 4 45 5 44 6 43 RG9 VSS 8 9 40 VDD RB5 10 39 11 38 RB4 RB3 RB2 RB1 RB0 12 37 13 36 14 35 15 34 16 33 47 2 42 7 41 VSS OSCO/RC15 OSCI/RC12 VDD D+/RG2 D-/RG3 VUSB3V3 VBUS/RF7 RF3 32 31 30 29 28 27 26 25 24
PIC24FJ128GC010 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Pin Function Pin Function 1 CTED4/PMD5/LCDBIAS2/CN63/RE5 33 AN30/SEG12/RP16/USBID/PMA12/CN71/RF3 2 PMD6/LCDBIAS1/CN64/RE6 34 VBUS/CN83/RF7 3 PMD7/LCDBIAS0/CN65/RE7 35 VUSB3V3 4 BGBUF2/AN17/OA1PB/C1IND/SEG0/RP21/T5CK/PMA5/CN8/ RG6 36 D-/CN73/RG3 5 VLCAP1/AN18/OA1NE/C1INC/RP26/PMA4/CN9/RG7 37 D+/CN72/RG2 6 VLCAP2/AN19/OA1ND/C2IND/RP19/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSCI/CLKI/CN23/RC12 8 AN4
PIC24FJ128GC010 FAMILY Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RE4 RE3 RE2 RG13 RG12 RG14 RE1 RE0 RA7 RA6 RG0 RG1 RF1 RF0 VBAT VCAP RD7 RD6 RD5 RD4 RD13 RD12 RD3 RD2 RD1 100-Pin TQFP (12 mm x 12 mm) RG15 1 75 VSS VDD 2 74 RC14 RE5 3 73 RC13 RE6 4 72 RD0 RE7 5 71 RD11 RC1 6 70 RD10 RC2 7 69 RD9 RC3 8 68 RD8 RC4 9 67 RA15 RG6 10 66 RA14 RG7 11 65 VSS RG8 12 64 OSCO/RC15 MCLR 13 63 OSCI/RC12 RG9
PIC24FJ128GC010 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function Pin Function 1 AN33/SEG50/CTED3/CN82/RG15 41 AN12/COM5/SEG18/T1CK/CTED2/PMA11/CN30/RB12 2 VDD 42 AN13/OA2PD/SEG19/DAC2/CTED1/PMA10/CN31/RB13 AN14/OA2NE/SEG8/RP14/CTED5/CTPLS/PMA1/CN32/RB14 3 CTED4/PMD5/LCDBIAS2/CN63/RE5 43 4 PMD6/LCDBIAS1/CN64/RE6 44 AN15/SEG9/RP29/T2CK/REFO/CTED6/PMA0/CN12/RB15 5 PMD7/LCDBIAS0/CN65/RE7 45 VSS 6 AN8/OA1NB/SEG32/RPI38/CN45/RC1 46 VDD 7 SEG51/RPI39
PIC24FJ128GC010 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES (CONTINUED) Pin Function Pin Function 81 AN47/OA1PE/SEG23/RP25/PMWR/CN13/RD4 91 82 AN48/OA1NB/SEG24/RP20/PMRD/CN14/RD5 92 AN23/SEG57/CN39/RA6 AN22/SEG58/PMA17/CN40/RA7 83 AN34/OA1PC/C3INB/SEG25/PMD14/CN15/RD6 93 COM3/PMD0/CN58/RE0 84 AN20/C3INA/SEG26/PMD15/CN16/RD7 94 COM2/PMD1/CN59/RE1 85 VCAP 95 SEG59/CTED11/PMA16/CN81/RG14 86 VBAT 96 SEG60/CN79/RG12 87 COM7/SEG27/VCMPST1/PMD11/CN68/RF0 97
PIC24FJ128GC010 FAMILY Pin Diagrams (Continued) 121-Pin BGA (10 mm x 10 mm, Top View) A B C 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 VBAT N/C RD12 RD2 RD1 N/C RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 N/C RC13 RD11 RC1 RE7 RE5 N/C N/C N/C RD6 RD13 RD0 N/C RD10 RC4 RC3 RG6 RC2 N/C RG1 N/C RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS N/C N/C VDD OSCI/ RC12 VSS OSCO/ RC15 RE8 RE9 RA0 N/C VD
PIC24FJ128GC010 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES Pin Function Pin Function A1 HLVDIN/SEG62/CTED8/PMD4/CN62/RE4 E1 AN16/SEG52/RPI41/PMCS2/CN48/RC4 A2 COM0/CTED9/PMD3/CN61/RE3 E2 AN9/OA1NC/SEG33/RPI40/CN47/RC3 A3 SEG61/CTED10/CN80/RG13 E3 BGBUF2/AN17/OA1PB/C1IND/SEG0/RP21/T5CK/PMA5/ CN8/RG6 A4 COM3/PMD0/CN58/RE0 E4 SEG51/RPI39/CN46/RC2 A5 SEG49/PMD8/CN77/RG0 E5 N/C A6 COM4/SEG47/VCMPST2/PMD10/CN69/RF1 E6 SEG46/PMD9/CN78/RG1 A7 VBAT E7 N/C
PIC24FJ128GC010 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED) Pin Function Pin Function J1 AN3/OA2OUT/C2INA/SEG4/VPIO/CN5/RB3 K7 AN14/OA2NE/SEG8/RP14/CTED5/CTPLS/PMA1/CN32/RB14 J2 AN2/OA2NC/CTCMP/C2INB/SEG5/RP13/T4CK/VMIO/ CTED13/CN4/RB2 K8 VDD J3 PGED2/AN7/COM6/SEG30/RP7/CN25/RB7 K9 AN29/SEG39/RP5/CN21/RD15 J4 AVDD K10 AN30/SEG12/RP16/USBID/PMA12/CN71/RF3 J5 SVDD K11 AN31/SEG40/RP30/CN70/RF2 J6 TCK/AN26/SEG31/CN34/RA1 L1 PGEC2/AN6/OA1PD/RP6/
PIC24FJ128GC010 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 33 3.0 CPU ....................................................................................................
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PIC24FJ128GC010 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ64GC006 • PIC24FJ128GC006 • PIC24FJ64GC010 • PIC24FJ128GC010 The PIC24FJ128GC010 family expands the capabilities of the PIC24F family by adding a complete selection of advanced analog peripherals to its existing digital features.
PIC24FJ128GC010 FAMILY 1.2 Advanced Analog Features The centerpiece of the PIC24FJ128GC010 family is the advanced analog block. This feature set provides application developers with all the tools they need for single chip applications that demand high analog performance. Included in the advanced analog block are: • A new 12-bit, pipelined A/D Converter (A/D) module.
PIC24FJ128GC010 FAMILY 1.6 Other Special Features • Peripheral Pin Select (PPS): The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ128GC010 family incorporates several different serial communication peripherals to handle a range of application requirements.
PIC24FJ128GC010 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GC010 FAMILY: 64-PIN Features PIC24FJ64GC006 Operating Frequency Program Memory (bytes) Program Memory (instructions) PIC24FJ128GC006 DC – 32 MHz 64K 128K 22,016 Data Memory (bytes) 44,032 8K Interrupt Sources (soft vectors/ NMI traps) 65 (61/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 53 Remappable Pins 30 (29 I/O, 1 input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Captur
PIC24FJ128GC010 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ128GC010 FAMILY: 100/121-PIN DEVICES Features PIC24FJ64GC010 Operating Frequency Program Memory (bytes) Program Memory (instructions) PIC24FJ128GC010 DC – 32 MHz 64K 128K 22,016 Data Memory (bytes) 44,032 8K Interrupt Sources (soft vectors/ NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 85 Remappable Pins 44 (32 I/O, 12 input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers)
PIC24FJ128GC010 FAMILY FIGURE 1-1: PIC24FJ128GC010 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (12 I/O) 16 16 8 Data Latch EDS and Table Data Access Control 23 DMA Controller Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic PORTB Address Latch (16 I/O) 16 23 16 16 Read AGU Write AGU Address Latch Program Memory/ Extended Data Space PORTC(1) (8 I/O) Data Latch 16 Address Bus EA MUX 24 16 Inst Latch Inst Register Instruction De
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer AN0 16 25 K2 I ANA AN1 15 24 K1 I ANA AN2 14 23 J2 I ANA AN3 13 22 J1 I ANA AN4 12 21 H2 I ANA AN5 11 20 H1 I ANA AN6 17 26 L1 I ANA AN7 18 27 J3 I ANA AN8 — 6 D1 I ANA AN9 — 8 E2 I ANA AN10 32 50 L11 I ANA ANA AN11 31 49 L10 I AN12 27 41 J7 I ANA AN13 28
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer AN41 44 70 D11 I ANA AN42 45 71 C11 I ANA AN43 46 72 D9 I ANA AN44 51 78 B9 I ANA AN45 — 79 A9 I ANA AN46 — 80 D8 I ANA AN47 52 81 C8 I ANA AN48 53 82 B8 I ANA AN49 8 14 F3 I ANA AVDD 19 30 J4 P — AVREF+ 16 25, 29 K2, K3 I ANA Pipeline A/D Reference Volta
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST ST CN9 5 11 F4 I CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 121-Pin BGA I/O Input Buffer 64-Pin TQFP/QFN 100-Pin TQFP CN50 49 76 A11 I ST CN51 50 77 A10 I ST CN52 51 78 B9 I ST CN53 42 68 E9 I ST CN54 43 69 E10 I ST CN55 44 70 D11 I ST CN56 45 71 C11 I ST CN57 — 79 A9 I ST CN58 60 93 A4 I ST CN59 61 94 B4 I ST CN60 62 98 B3 I ST CN61 63 99 A2 I ST CN62 64 100 A1
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CS1 45 71 C11 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe (shared with PMA14). CS2 44 70 D11 O — Parallel Master Port Chip Select 2 Strobe (shared with PMA15). CTCMP 14 23 J2 I ANA CTMU Comparator 2 Input (Pulse mode). CTMU External Edge Inputs.
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer OA1NA 12 21 H2 I ANA OA1NB 53 82 B8 I ANA OA1NC — 8 E2 I ANA OA1ND 6 12 F2 I ANA OA1NE 5 11 F4 I ANA OA1OUT 11 20 H1 O — OA1PA 8 14 F3 I ANA OA1PB 4 10 E3 I ANA OA1PC 54 83 D7 I ANA OA1PD 17 26 L1 I ANA OA1PE 52 81 C8 I ANA OA2NA 46 72 D9 I ANA OA2N
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator 121-Pin BGA I/O Input Buffer 50 L11 O — 49 L10 O — 28 42 L7 O — PMA11 27 41 J7 O — PMA12 33 51 K10 O — PMA13 42 68 E9 O — PMA14 45 71 C11 O — PMA15 44 70 D11 O — PMA16 — 95 C4 O — PMA17 — 92 B5 O — PMA18 — 40 K6 O — PMA19 — 19 G2 O — PMA20 — 59 G10 O — PMA21 — 60 G11 O — PMA22 — 66 E11 O — PMACK1 50 77 A10
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RA0 — 17 G3 I/O ST RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 121-Pin BGA I/O Input Buffer 72 D9 I/O ST 76 A11 I/O ST 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RG0 — 90 A5 I/O ST RG1 — 89 E6 I/O ST RG2 37 57 H10 I/O ST RG3 36 56 J11 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RP0 16 25 K
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 121-Pin BGA I/O Input Buffer 64-Pin TQFP/QFN 100-Pin TQFP RPI32 — 40 K6 I ST RPI33 — 18 G1 I ST RPI34 — 19 G2 I ST RPI35 — 67 E8 I ST RPI36 — 66 E11 I ST RPI37 48 74 B11 I ST RPI38 — 6 D1 I ST RPI39 — 7 E4 I ST RPI40 — 8 E2 I ST RPI41 — 9 E1 I ST RPI42 — 79 A9 I ST ST Description Remappable Peripheral (input on
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer SEG21 50 77 A10 O — SEG22 51 78 B9 O — SEG23 52 81 C8 O — SEG24 53 82 B8 O — SEG25 54 83 D7 O — SEG26 55 84 C7 O — SEG27 58 87 B6 O — SEG28 — 61 G9 O — SEG29 — 60 G11 O — SEG30 18 27 J3 O — SEG31 — 38 J6 O — SEG32 — 6 D1 O — SEG33 — 8 E2 O — S
PIC24FJ128GC010 FAMILY TABLE 1-3: PIC24FJ128GC010 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number/Grid Locator Pin Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer Description SOSCI 47 73 C10 I ANA Secondary Oscillator Input. SOSCO 48 74 B11 O ANA Secondary Oscillator Output. SVDD 26 37 J5 P — SVREF+ 24 35 K5 I ANA Sigma-Delta A/D Converter Voltage Reference (high). SVREF- 25 36 L5 I ANA Sigma-Delta A/D Converter Voltage Reference (low).
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 32 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All analog power pins (AVDD, SVDD, AVSS and SVSS), regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • The USB transceiver supply, VUSB3V3, regardless of whether or not the USB module is used (see Section 2.
PIC24FJ128GC010 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins is required. This includes digital supply (VDD and VSS) and all analog supplies (AVDD, SVDD, AVSS and SVSS). Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher.
PIC24FJ128GC010 FAMILY 2.4 FIGURE 2-3: Voltage Regulator Pin (VCAP) A low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the output voltage of the on-chip voltage regulator. The VCAP pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specification can be used. FREQUENCY vs.
PIC24FJ128GC010 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24FJ128GC010 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FJ128GC010 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. All PIC24F devices will have either one or more ADnPCFG registers or several ANSx registers (one for each port); no device will have both.
PIC24FJ128GC010 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “CPU with Extended Data Space (EDS)” (DS39732). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 Data RAM Up to 0x7FFF PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 Address Latch 23 16 RAGU WAGU Address Latch EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 Literal Data Program Memory/
PIC24FJ128GC010 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 9 Program Counter Table Memory Page Address Register 0 Data Space Read Page Register DSRPAG 8 0 Data Space Write Page Register DSWPAG 15 0 RCOUNT 15 Stack Pointer Limit Value Register SRH SRL Repeat Loop Counter Register 0 — — —
PIC24FJ128GC010 FAMILY 3.
PIC24FJ128GC010 FAMILY REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 =
PIC24FJ128GC010 FAMILY 3.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
PIC24FJ128GC010 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and buses. This architecture also allows direct access of program memory from the Data Space (DS) during code execution. 4.1 Program Memory Space The program address memory space of the PIC24FJ128GC010 family devices is 4M instructions.
PIC24FJ128GC010 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In PIC24FJ128GC010 family devices, the top four words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration register. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GC010 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1.
PIC24FJ128GC010 FAMILY 4.2 Note: The upper half of data memory address space (8000h to FFFFh) is used as a window into the Extended Data Space (EDS). This allows the microcontroller to directly access a greater range of data beyond the standard 16-bit address range. EDS is discussed in detail in Section 4.2.5 “Extended Data Space (EDS)”. Data Memory Space This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ128GC010 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® MCUs and improve Data Space memory usage efficiency, the PIC24F instruction set supports both word and byte operations.
2012-2013 Microchip Technology Inc.
File Addr Name ICN REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CNPD2 0058 CN31PDE CN30PDE — — — — CN25PDE CN24PDE CN23PDE CN22PDE Bit 5 Bit 4 Bit 3 CN5PDE CN4PDE CN3PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) Bit 2 Bit 1 CN63PDE CN62PDE CN61PDE CN60PDE CN59PDE CN58PDE CNPD5 005E CN79PDE(1) CN78PDE(1) CN77PDE(1) CN76PDE(1) CN75PDE(1) CN74PDE(1) CN
2012-2013 Microchip Technology Inc.
File Name INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) Bit 0 All Resets — — 4440 HLVDIP1 HLVDIP0 0004 — — 4440 — — — 4440 — — — — 4400 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 0044 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 0044 — — — — LCDIP2 LCDIP1 LCDIP0 4004 — SDA1IP2 SDA1IP1 SDA1IP0 — AMP2IP2 AMP2IP1 AMP2IP0 0444 — — JTAGIP2 JTAGIP1 JTAGIP0 — — — — 0040 ILR0 — Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit
2012-2013 Microchip Technology Inc.
OUTPUT COMPARE REGISTER MAP Bit 15 0000 Output Compare 1 Register 0000 OC1TMR 0198 Timer Value 1 Register FLTOUT FLTTRIEN OCTSEL2 OCTSEL1 OCTSEL0 OCINV — DCB1 OC32 ENFLT0 OCFLT2 OCFLT1 OCTRIG TRIGSTAT OCTRIS 0000 0196 OCSIDL ENFLT1 DCB0 OCM0 OC1R — ENFLT2 Bit 5 OCM1 Output Compare 1 Secondary Register DCB1 Bit 6 OCM2 0194 — Bit 7 TRIGMODE OC1RS OCINV Bit 8 OCFLT0 — FLTMD OCTSEL2 OCTSEL1 OCTSEL0 Bit 9 All Resets 0192 FLTMD OCSIDL Bit 10 Bit 0 0190 OC2CON2 019C
2012-2013 Microchip Technology Inc.
File Name Addr UART REGISTER MAPS Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 — UTXBRK UTXEN UTXBF TRMT Bit 0 All Resets PDSEL0 STSEL 0000 OERR URXDA 0110 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR U1MODE 0220 U1STA 0222 U1TXREG 0224 — — — — — — — Transmit Register xxxx U1RXREG 0226 — — — — — — — Receive Register 0
2012-2013 Microchip Technology Inc.
File Name Addr PORTC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4(1) Bit 3(1) Bit 2(1) Bit 1(1) Bit 0 All Resets TRISC 02D0 TRISC15 — — TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — 901E PORTC 02D2 RC15(2,3) RC14(4) RC13(4) RC12(2) — — — — — — — RC4 RC3 RC2 RC1 — xxxx LATC 02D4 LATC15 — — LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx ODCC 02D6 ODC15 — — ODC12 — — — —
2012-2013 Microchip Technology Inc.
File Name DAC REGISTER MAP Addr Bit 15 Bit 14 DAC1CON 0440 DACEN — DAC1DAT 0442 DAC2CON 0444 DAC2DAT 0446 Bit 13 Bit 12 DACSIDL DACSLP Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 DACFM — — DACTRIG — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DACTSEL4 DACTSEL3 DACTSEL2 DACTSEL1 DACTSEL0 DACREF1 DACREF0 DAC1 Input Value Register DACEN — DACSIDL DACSLP DACFM — — DACTRIG — All Resets 0000 0000 DACTSEL4 DACTSEL3 DACTSEL2 DACTSEL1 DACTSEL0 DACREF1 DACREF0 DAC2 Input Value Register
2012-2013 Microchip Technology Inc.
12-BIT PIPELINE A/D CONVERTER REGISTER MAP (CONTINUED) 2012-2013 Microchip Technology Inc.
2012-2013 Microchip Technology Inc.
File Name 12-BIT PIPELINE A/D CONVERTER REGISTER MAP (CONTINUED) Bit 13 Bit 12 Bit 11 — — — Bit 7 Bit 6 Bit 5 — — ACEN ACIE — Bit 3 Bit 2 — — — — 0000 050E — — ACCONL 050C — — ACRESH 0512 A/D Accumulation High Result Register (bits<31-16>) ACRESL 0510 A/D Accumulation Low Result Register (bits<15-0>) ADCHITH 0516 CHH31 CHH30 CHH29 CHH28 CHH27 CHH26 CHH25 CHH24 CHH23 CHH22 CHH21 CHH20 CHH19 CHH18 CHH17 CHH16 0000 ADCHITL 0514 CHH15 CHH14 CHH13 CHH12
2012-2013 Microchip Technology Inc.
File Name USB OTG REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 U1OTGIR 0480 — — — — — — — — IDIF T1MSECIF LSTATEIF U1OTGIE 0482 — — — — — — — — IDIE T1MSECIE LSTATEIE U1OTGSTAT 0484 — — — — — — — — ID — LSTATE — U1OTGCON 0486 — — — — — — — — DPPULUP DMPULUP U1PWRC 0488 — — — — — — — — UACTPND — — 048A(1) — — — — — — — — STALLIF — — — — — — — — — STALLIF — — — — — — — — — — —
2012-2013 Microchip Technology Inc.
File Name LCD CONTROLLER REGISTER MAP (CONTINUED) Addr Bit 15 LCDDATA13 05AA S31C3(1) LCDDATA14 05AC S47C3 Bit 14 S30C3 Bit 13 Bit 12 S29C3(1) S28C3(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S27C3 S26C3 S25C3 S24C3 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 All Resets 0000 S46C3(1) S45C3(1) S44C3(1) S43C3(1) S42C3(1) S41C3(1) S40C3(1) S39C3(1) S38C3(1) S37C3(1) S36C3(1) S35C3(1) S34C3(1) S33C3(1) S32C3(1) 0000 S61C3(1) S60C3(1)
2012-2013 Microchip Technology Inc.
File Name COMPARATORS REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 C3EVT C2EVT C1EVT CMSTAT 0630 CMIDL — — — — CVRCON 0632 — — — — — CM1CON 0634 CON COE CPOL — — — CEVT CM2CON 0636 CON COE CPOL — — — CM3CON 0638 CON COE CPOL — — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 — — — — — C3OUT C2OUT C1OUT CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 COUT EVPOL1 EVPOL0 — CREF — —
2012-2013 Microchip Technology Inc.
PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06C0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 RPOR1 06C2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 RPOR2 06C4 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) — — RP
2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) The Extended Data Space (EDS) allows PIC24F devices to address a much larger range of data than would otherwise be possible with a 16-bit address range. EDS includes any additional internal data memory not directly accessible by the lower 32-Kbyte data address space and any external memory through the Enhanced Parallel Master Port (EPMP). In addition, EDS also allows read access to the program memory space.
PIC24FJ128GC010 FAMILY 4.2.5.1 Data Read from EDS In order to read the data from the EDS space, first, an Address Pointer is set up by loading the required EDS page number into the DSRPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, the EDS window is enabled by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed EDS location can be read.
PIC24FJ128GC010 FAMILY 4.2.5.2 Data Write into EDS In order to write data to EDS space, such as in EDS reads, an Address Pointer is set up by loading the required EDS page number into the DSWPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, then the EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written.
PIC24FJ128GC010 FAMILY TABLE 4-41: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSRPAG (Data Space Read Register) DSWPAG (Data Space Write Register) Source/Destination Address While Indirect Addressing x(1) x(1) 0000h to 1FFFh 000000h to 001FFFh 2000h to 7FFFh 002000h to 007FFFh 001h 001h 008000h to 00FFFEh 002h 002h 010000h to 017FFEh 003h • • • • • 1FFh 003h • • • • • 1FFh 018000h to 0187FEh • • • • FF8000h to FFFFFEh 000h 000h 8000h to FFFFh EPMP Memory Space Address Erro
PIC24FJ128GC010 FAMILY 4.3 4.3.1 Interfacing Program and Data Memory Spaces ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The PIC24F architecture uses a 24-bit wide program space and 16-bit wide Data Space.
PIC24FJ128GC010 FAMILY FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter Program Counter 0 0 23 Bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select Program Space Visibility(1) (Remapping) 1-Bit 0 EA 1 1/0 DSRPAG<7:0> 8 Bits 15 Bits 23 Bits User/Configuration Space Select Byte Select Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory.
PIC24FJ128GC010 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through Data Space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ128GC010 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING EDS The upper 32 Kbytes of Data Space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the Data Space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the Data Space occurs when the MSb of EA is ‘1’ and the DSRPAG<9> is also ‘1’.
PIC24FJ128GC010 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1 Program Space DSRPAG 202h 23 15 Data Space 0 000000h 0000h Data EA<14:0> 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window FFFFh 7FFFFEh FIGURE 4-11: ...while the lower 15 bits of the EA specify an exact address within the EDS area.
PIC24FJ128GC010 FAMILY 5.0 DIRECT MEMORY ACCESS CONTROLLER (DMA) This data sheet summarizes the features of the PIC24FJ128GC010 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24F Family Reference Manual”, “Direct Memory Access Controller (DMA)” (DS39742). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY 5.1 Summary of DMA Operations The DMA controller is capable of moving data between addresses according to a number of different parameters. Each of these parameters can be independently configured for any transaction. In addition, any or all of the DMA channels can independently perform a different transaction at the same time.
PIC24FJ128GC010 FAMILY FIGURE 5-2: TYPES OF DMA DATA TRANSFERS Peripheral to Memory Memory to Peripheral SFR Area SFR Area DMADSTn DMASRCn Data RAM 07FFh 0800h Data RAM DMAL DMA RAM Area DMA RAM Area 07FFh 0800h DMAL DMADSTn DMASRCn DMAH DMAH Peripheral to Peripheral Memory to Memory SFR Area SFR Area DMASRCn DMADSTn Data RAM DMA RAM Area 07FFh 0800h DMAL 07FFh 0800h Data RAM DMA RAM Area DMAL DMASRCn DMADSTn DMAH Note: DMAH Relative sizes of memory areas are not shown to s
PIC24FJ128GC010 FAMILY 5.1.6 CHANNEL PRIORITY Each DMA channel functions independently of the others, but also competes with the others for access to the data and DMA buses. When access collisions occur, the DMA controller arbitrates between the channels using a user-selectable priority scheme. Two schemes are available: • Round Robin: When two or more channels collide, the lower numbered channel receives priority on the first collision.
PIC24FJ128GC010 FAMILY REGISTER 5-1: DMACON: DMA ENGINE CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DMAEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PRSSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DMAEN: DMA Module Enable bit 1 = Enables module 0 = Disables module and terminates all active DMA operation(s) bit 14-1
PIC24FJ128GC010 FAMILY REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER U-0 — U-0 — U-0 — r-0 r U-0 — R/W-0 NULLW R/W-0 RELOAD(1) R/W-0 CHREQ(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMODE1 bit 7 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN bit 0 Legend: R = Readable bit r = Reserved bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 bit 12 Unimplemen
PIC24FJ128GC010 FAMILY REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER R-0 DBUFWF (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 bit 15 bit 8 R/W-0 R/W-0 (1,2) HIGHIF LOWIF (1,2) R/W-0 (1) DONEIF R/W-0 HALFIF (1) R/W-0 (1) OVRUNIF U-0 U-0 R/W-0 — — HALFEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkno
PIC24FJ128GC010 FAMILY TABLE 5-1: DMA TRIGGER SOURCES CHSEL<5:0> Trigger (Interrupt) CHSEL<5:0> Trigger (Interrupt) 000000 (Unimplemented) 100000 UART2 Transmit 000001 DAC2 100001 UART2 Receive 000010 LCD 100010 External Interrupt 2 000011 UART4 Transmit 100011 Timer5 000100 UART4 Receive 100100 Timer4 000101 UART4 Error 100101 Output Compare 4 000110 UART3 Transmit 100110 Output Compare 3 000111 UART3 Receive 100111 DMA Channel 2 001000 UART3 Error 101000 DAC1 0010
PIC24FJ128GC010 FAMILY 6.0 Note: RTSP is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time and erase program memory in blocks of 512 instructions (1536 bytes) at a time. FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ128GC010 FAMILY 6.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.
PIC24FJ128GC010 FAMILY REGISTER 6-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/S-0, HC(1) R/W-0(1) R-0, HSC(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — R/W-0(1) U-0 — NVMOP3 (2) R/W-0(1) R/W-0(1) (2) NVMOP2 NVMOP1 (2) R/W-0(1) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FJ128GC010 FAMILY 6.5 4. Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (Waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. 6.5.1 5. PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time.
PIC24FJ128GC010 FAMILY EXAMPLE 6-2: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVM
PIC24FJ128GC010 FAMILY 6.5.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes (MSBs) of the Flash address. The TBLWTL and TBLWTH instructions write the desired data into the EXAMPLE 6-5: write latches and specify the lower 16 bits of the program memory address to write to.
PIC24FJ128GC010 FAMILY 7.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Reset” (DS39712). The information in this data sheet supersedes the information in the FRM. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FJ128GC010 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 (1) TRAPR U-0 (1) IOPUWR R/W-0 — RETEN U-0 (2) R/W-0 (1) — DPSLP R/W-0 (1) CM R/W-0 PMSLP(3) bit 15 bit 8 R/W-0 R/W-0 (1) (1) SWR EXTR R/W-0 R/W-0 (4) SWDTEN R/W-0 (1) (1) WDTO SLEEP R/W-0 R/W-1 R/W-1 (1) (1) POR(1) IDLE BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
PIC24FJ128GC010 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER (CONTINUED) bit 5 SWDTEN: Software Enable/Disable of WDT bit(4) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit(1) 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake from Sleep Flag bit(1) 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit(1) 1 = Device has been in Idle mode 0 = Device has not been in Idle mo
PIC24FJ128GC010 FAMILY REGISTER 7-2: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — r-0 — r R/CO-1 VDDBOR (1) R/CO-1 (1,2) VDDPOR R/CO-1 (1,3) VBPOR R/CO-0 VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented
PIC24FJ128GC010 FAMILY 7.1 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers.
PIC24FJ128GC010 FAMILY TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS SYSRST Delay System Clock Delay EC TPOR + TSTARTUP + TRST — Reset Type POR BOR Clock Source Notes 1, 2, 3 ECPLL TPOR + TSTARTUP + TRST TLOCK 1, 2, 3, 5 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST 1, 2, 3, 4 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5 FRC, FRCDIV TPOR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7 FRCPLL TPOR + TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6 LPRC TPOR + TSTARTUP + TR
PIC24FJ128GC010 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Interrupts” (DS39707). The information in this data sheet supersedes the information in the FRM. The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU.
PIC24FJ128GC010 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap V
PIC24FJ128GC010 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority A/D (12-Bit Pipeline) 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> A/D (Sigma-Delta) 105 0000E6h 0001E6h IFS6<9> IEC6<9> IPC26<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> DAC
PIC24FJ128GC010 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority Enhanced Parallel Master Port (EPMP) 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4> Real-Time Clock and Calendar (RTCC) 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8> SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> SPI2 Error 32 000054h 000154h
PIC24FJ128GC010 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FJ128GC010 family of devices implements a total of 44 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS7 IEC0 through IEC7 IPC0 through IPC13, ICP15, ICP16, ICP18 through ICP23, ICP25, ICP26 and ICP29 • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2.
PIC24FJ128GC010 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 IPL2 R/W-0 (2,3) IPL1 (2,3) R/W-0 IPL0 (2,3) R-0 (1) RA R/W-0 (1) N R/W-0 (1) OV R/W-0 Z R/W-0 (1) bit 7 C(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>:
PIC24FJ128GC010 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — R/C-0 IPL3 (1) r-1 U-0 U-0 r — — bit 7 bit 0 Legend: r = Reserved bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU
PIC24FJ128GC010 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting
PIC24FJ128GC010 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector
PIC24FJ128GC010 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GC010 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2012-2013 Micr
PIC24FJ128GC010 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIF: UART2 Transmitter Interrupt
PIC24FJ128GC010 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2012-2013 Microchip Techno
PIC24FJ128GC010 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IF: DMA
PIC24FJ128GC010 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — RTCIF DMA5IF — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-
PIC24FJ128GC010 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 DAC2IF DAC1IF CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DAC2IF: DAC Converter 2 Interrupt Flag Status bit 1 = Interrupt request has occurr
PIC24FJ128GC010 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — IC9IF OC9IF — — U4TXIF U4RXIF bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIF USB1IF — — U3TXIF U3RXIF U3ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 IC9IF: Input Capture Channel
PIC24FJ128GC010 FAMILY REGISTER 8-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — FSTIF SDA1IF AMP2IF bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 AMP1IF — — LCDIF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 FSTIF: FRC Self-Tune Interrupt Flag Status bit 1 = Interr
PIC24FJ128GC010 FAMILY REGISTER 8-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIF: JTAG Controller Interrupt Flag Status bit 1 = Interrupt request has occurred
PIC24FJ128GC010 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit
PIC24FJ128GC010 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY REGISTER 8-14: R/W-0 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2TXIE U2RXIE R/W-0 (1) INT2IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 IC8IE IC7IE U-0 — R/W-0 (1) INT1IE R/W-0 R/W-0 R/W-0 R/W-0 CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter
PIC24FJ128GC010 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 4 INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable
PIC24FJ128GC010 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IE:
PIC24FJ128GC010 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — RTCIE DMA5IE — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/
PIC24FJ128GC010 FAMILY REGISTER 8-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 DAC2IE DAC1IE CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DAC2IE: DAC Converter 2 Interrupt Enable bit 1 = Interrupt request is enabled
PIC24FJ128GC010 FAMILY REGISTER 8-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — IC9IE OC9IE — — U4TXIE U4RXIE bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIE USBIE — — U3TXIE U3RXIE U3ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 IC9IE: Input Capture Channe
PIC24FJ128GC010 FAMILY REGISTER 8-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — FSTIE SDA1IE AMP2IE bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 AMP1IE — — LCDIE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 FSTIE: FRC Self-Tune Interrupt Enable bit 1 = Interrup
PIC24FJ128GC010 FAMILY REGISTER 8-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIE: JATG Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt r
PIC24FJ128GC010 FAMILY REGISTER 8-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T
PIC24FJ128GC010 FAMILY REGISTER 8-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T
PIC24FJ128GC010 FAMILY REGISTER 8-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GC010 FAMILY REGISTER 8-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP2 DMA1IP1 DMA1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: D
PIC24FJ128GC010 FAMILY REGISTER 8-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GC010 FAMILY REGISTER 8-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input C
PIC24FJ128GC010 FAMILY REGISTER 8-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T
PIC24FJ128GC010 FAMILY REGISTER 8-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ128GC010 FAMILY REGISTER 8-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Pri
PIC24FJ128GC010 FAMILY REGISTER 8-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12
PIC24FJ128GC010 FAMILY REGISTER 8-31: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12
PIC24FJ128GC010 FAMILY REGISTER 8-32: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA4IP2 DMA4IP1 DMA4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PMPIP2 PMPIP1 PMPIP0 — OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DM
PIC24FJ128GC010 FAMILY REGISTER 8-33: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 E
PIC24FJ128GC010 FAMILY REGISTER 8-34: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4
PIC24FJ128GC010 FAMILY REGISTER 8-35: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — DMA5IP2 DMA5IP1 DMA5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Cale
PIC24FJ128GC010 FAMILY REGISTER 8-36: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CR
PIC24FJ128GC010 FAMILY REGISTER 8-37: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bit
PIC24FJ128GC010 FAMILY REGISTER 8-38: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DAC2IP2 DAC2IP1 DAC2IP0 — DAC1IP2 DAC1IP1 DAC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DAC2IP<2:0>
PIC24FJ128GC010 FAMILY REGISTER 8-39: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>
PIC24FJ128GC010 FAMILY REGISTER 8-40: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERIP<2:0>: UART4 Error Interrupt
PIC24FJ128GC010 FAMILY REGISTER 8-41: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U4TXIP<2:0>: UART4 Transmitter Inte
PIC24FJ128GC010 FAMILY REGISTER 8-42: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC9IP<2:0>: Input Capture Channel 9 Inter
PIC24FJ128GC010 FAMILY REGISTER 8-43: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — AMP1IP2 AMP1IP1 AMP1IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LCDIP2 LCDIP1 LCDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AMP1IP<2:0>: Op Amp 1 Interrupt Priori
PIC24FJ128GC010 FAMILY REGISTER 8-44: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — FSTIP2 FSTIP1 FSTIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SDA1IP2 SDA1IP1 SDA1IP0 — AMP2IP2 AMP2IP1 AMP2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 FSTIP<2:0>:
PIC24FJ128GC010 FAMILY REGISTER 8-45: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — JTAGIP2 JTAGIP1 JTAGIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 JTAGIP<2:0>: JTAG Interrupt Priority bits 111 = Interrupt i
PIC24FJ128GC010 FAMILY REGISTER 8-46: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0 r-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ r VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Re
PIC24FJ128GC010 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ128GC010 FAMILY 9.
PIC24FJ128GC010 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHZ PLL. Refer to Section 9.
PIC24FJ128GC010 FAMILY 9.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock Switching Operation” for more information.
PIC24FJ128GC010 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FJ128GC010 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 PLLEN — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts c
PIC24FJ128GC010 FAMILY REGISTER 9-3: R/W-0 OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 STEN — R/W-0 STSIDL R/W-0 STSRC (1) R-0 R/W-0 R-0 R/W-0 STLOCK STLPOL STOR STORPOL bit 15 bit 8 U-0 U-0 — — R/W-0 TUN5 (2) R/W-0 (2) TUN4 R/W-0 (2) TUN3 R/W-0 TUN2 R/W-0 (2) TUN1 (2) R/W-0 TUN0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 STEN: FRC Self-Tu
PIC24FJ128GC010 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits.
PIC24FJ128GC010 FAMILY A recommended code sequence for a clock switch includes the following: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write the new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24FJ128GC010 FAMILY 9.6 TABLE 9-2: Oscillator Modes and USB Operation Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled and not in a suspended operating state. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source.
PIC24FJ128GC010 FAMILY 9.6.1 CONSIDERATIONS FOR USB OPERATION When using the USB On-The-Go module in PIC24FJ128GC010 family devices, users must always observe these rules in configuring the system clock: • The oscillator modes listed in Table 9-3 are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. • For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements.
PIC24FJ128GC010 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referen
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 170 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 10.0 POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24FJ devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Power-Saving Features with Deep Sleep” (DS39727). Note: The PIC24FJ128GC010 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FJ128GC010 FAMILY TABLE 10-2: EXITING POWER SAVING MODES Exit Conditions INT0 All POR MCLR RTCC Alarm WDT All VDD Restore(2) Code Execution Resumes Idle Y Y Y Y Y Y Y N/A Next instruction Sleep (all modes) Y Y Y Y Y Y Y N/A (1) Mode Interrupts Resets Deep Sleep N Y N Y Y Y Y N/A Reset vector Retention Deep Sleep N Y N Y Y Y Y(1) N/A Next instruction VBAT N N N N N N N Y Note 1: 2: 10.1.1 Deep Sleep WDT.
PIC24FJ128GC010 FAMILY 10.1.2 HARDWARE-BASED POWER-SAVING MODE The hardware-based VBAT mode does not require any action by the user during code development. Instead, it is a hardware design feature that allows the microcontroller to retain critical data (using the DSGPRx registers) and maintain the RTCC when VDD is removed from the application. This is accomplished by supplying a backup power source to a specific power pin. VBAT mode is described in more detail in Section 10.5 “Vbat Mode”. 10.1.
PIC24FJ128GC010 FAMILY 10.4 Deep Sleep Mode Deep Sleep mode provides the lowest levels of power consumption available from the Instruction-Based modes. PIC24FJ128GC010 family devices have two Deep Sleep modes: Legacy Deep Sleep, found in other PIC24F devices, and Retention Deep Sleep, described below. Deep Sleep modes have these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum.
PIC24FJ128GC010 FAMILY Any time the DSEN bit is set, all bits in the DSWAKE register will be automatically cleared. EXAMPLE 10-2: The sequence for exiting Deep Sleep mode is: 1. THE REPEAT SEQUENCE Example 1: mov mov mov #8000, w2 w2, DSCON w2, DSCON ; enable DS ; second write required to actually write to DSCON 3. Example 2: bset nop nop nop bset DSCON, #15 DSCON, #15 10.4.3 4.
PIC24FJ128GC010 FAMILY Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON<1>), are reset.
PIC24FJ128GC010 FAMILY 10.5 VBAT Mode This mode represents the lowest power state that the microcontroller can achieve and still resume operation. VBAT mode is automatically triggered when the microcontroller’s main power supply on VDD fails. When this happens, the microcontroller’s on-chip power switch connects to a backup power source, such as a battery, supplied to the VBAT pin. This maintains a few key systems at an extremely low-power draw until VDD is restored.
PIC24FJ128GC010 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 10-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — r-0 R/W-0 (2) r DSBOR R/C-0, HS RELEASE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit r = Reserved bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enabl
PIC24FJ128GC010 FAMILY REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 DSFLT — — DSWDT DSRTCC DSMCLR — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Rea
PIC24FJ128GC010 FAMILY REGISTER 10-3: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 r-0 — — — r R/CO-1 R/CO-1 VDDBOR(1) VDDPOR(1,2) R/CO-1 R/CO-0 VBPOR(1,3) VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented:
PIC24FJ128GC010 FAMILY 10.6 Clock Frequency and Clock Switching In Run and Idle modes, all PIC24FJ devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSCx bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 “Oscillator Configuration”. 10.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 182 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). The information in this data sheet supersedes the information in the FRM. All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the Parallel I/O ports.
PIC24FJ128GC010 FAMILY 11.1.1 I/O PORT WRITE/READ TIMING 11.2 One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 11.1.2 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx and TRISx registers for data control, each port pin can also be individually configured for either a digital or open-drain output.
PIC24FJ128GC010 FAMILY TABLE 11-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT Port or Pin Tolerated Input Description 5.5V Tolerates input levels above VDD; useful for most standard logic. VDD Only VDD input levels are tolerated.
PIC24FJ128GC010 FAMILY REGISTER 11-1: R/W-1 ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER R/W-1 (1) ANSA15 ANSA14 U-0 (1) — U-0 — U-0 — R/W-1 R/W-1 (1) ANSA10 ANSA9 (1) U-0 — bit 15 bit 8 R/W-1 ANSA7 (1) R/W-1 R/W-1 R/W-1 ANSA6(1) ANSA5(1) ANSA4(1) U-0 — U-0 R/W-1 U-0 — ANSA1(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 ANSA<15:14>: Analog Function Sele
PIC24FJ128GC010 FAMILY REGISTER 11-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 ANSB15 ANSB14 ANSB13 ANSB12 — — — — bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 ANSB<15:12>: Analog Function Selection bit
PIC24FJ128GC010 FAMILY REGISTER 11-4: R/W-1 ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER R/W-1 ANSD15(1) ANSD14 R/W-1 (1) R/W-1 (1) ANSD13 ANSD12 (1) R/W-1 R/W-1 R/W-1 R/W-1 ANSD11 ANSD10 ANSD9 ANSD8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 — ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 ANSD<15:
PIC24FJ128GC010 FAMILY REGISTER 11-6: ANSF: PORTF ANALOG FUNCTION SELECTION REGISTER U-0 U-0 R/W-1 U-0 U-0 U-0 U-0 R/W-1 — — ANSF13(1) — — — — ANSF8(1) bit 15 bit 8 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 ANSF7 — ANSF5 ANSF4 ANSF3 ANSF2(1) — ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 ANSF13: Analog Function
PIC24FJ128GC010 FAMILY REGISTER 11-7: ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER R/W-1 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 ANSG15(1) — — — — — ANSG9 ANSG8 bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSG7 ANSG6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ANSG15: Analog Function Selection bit(1) 1 = Pin is configured in Analog mode; I/O port
PIC24FJ128GC010 FAMILY 11.3 Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the PIC24FJ128GC010 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled.
PIC24FJ128GC010 FAMILY 11.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code, or a complete redesign, may be the only option.
PIC24FJ128GC010 FAMILY 11.4.3.1 Input Mapping The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 11-8 through Register 11-26). TABLE 11-3: Each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripherals.
PIC24FJ128GC010 FAMILY 11.4.3.2 Output Mapping corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 11-4). In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
PIC24FJ128GC010 FAMILY 11.4.3.3 Mapping Limitations 11.4.4.1 The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention, caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts.
PIC24FJ128GC010 FAMILY 11.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state.
PIC24FJ128GC010 FAMILY 11.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ128GC010 family of devices implements a total of 35 registers for remappable peripheral configuration: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 11.4.4.1 “Control Register Lock” for a specific command sequence.
PIC24FJ128GC010 FAMILY REGISTER 11-10: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign Ex
PIC24FJ128GC010 FAMILY REGISTER 11-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ128GC010 FAMILY REGISTER 11-14: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0
PIC24FJ128GC010 FAMILY REGISTER 11-16: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC9R<5:0>: Assign Input
PIC24FJ128GC010 FAMILY REGISTER 11-18: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 x = Bit is unknown Unimple
PIC24FJ128GC010 FAMILY REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ128GC010 FAMILY REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ128GC010 FAMILY REGISTER 11-24: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimple
PIC24FJ128GC010 FAMILY REGISTER 11-26: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC21R1 MDC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemente
PIC24FJ128GC010 FAMILY REGISTER 11-27: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ128GC010 FAMILY REGISTER 11-29: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimpleme
PIC24FJ128GC010 FAMILY REGISTER 11-31: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ128GC010 FAMILY REGISTER 11-33: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ128GC010 FAMILY REGISTER 11-35: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ128GC010 FAMILY REGISTER 11-37: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ128GC010 FAMILY REGISTER 11-39: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ128GC010 FAMILY REGISTER 11-41: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ128GC010 FAMILY 12.0 Figure 12-1 presents a block diagram of the 16-bit timer module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Timers” (DS39704). The information in this data sheet supersedes the information in the FRM. Note: To configure Timer1 for operation: 1. 2. 3. 4.
PIC24FJ128GC010 FAMILY T1CON: TIMER1 CONTROL REGISTER(1) REGISTER 12-1: R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 — TSIDL — — — TIECS1 R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 U-0 — R/W-0 TSYNC R/W-0 TCS TON bit 15 U-0 — R/W-0 TIECS0 bit 8 bit 7 U-0 — bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Uni
PIC24FJ128GC010 FAMILY 13.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Timers” (DS39704). The information in this data sheet supersedes the information in the FRM. The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent, 16-bit timers with selectable operating modes.
PIC24FJ128GC010 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TCY TCKPS<1:0> TMRCK 2 SOSC Input LPRC Input Prescaler 1, 8, 64, 256 Gate Sync TIECS<1:0> TGATE TGATE(2) TCS(2) 1 Q 0 Q Set T3IF (T5IF) PR3 (PR5) Equal D CK PR2 (PR4) Comparator A/D Event Trigger(3) MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be se
PIC24FJ128GC010 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK (T4CK) TCY TMRCK TON TCKPS<1:0> 2 SOSC Input LPRC Input Prescaler 1, 8, 64, 256 Gate Sync TGATE TIECS<1:0> 1 Set T2IF (T4IF) TGATE(1) TCS(1) Q D Q CK 0 Reset Equal TMR2 (TMR4) Sync Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
PIC24FJ128GC010 FAMILY TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) REGISTER 13-1: R/W-0 U-0 TON — R/W-0 TSIDL U-0 — U-0 — U-0 R/W-0 R/W-0 — TIECS1(2) TIECS0(2) bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32 (3) U-0 — R/W-0 (2) TCS bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Star
PIC24FJ128GC010 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) bit 3 T32: 32-Bit Timer Mode Select bit(3) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
PIC24FJ128GC010 FAMILY TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(1) REGISTER 13-2: R/W-0 U-0 TON(2) — R/W-0 TSIDL (2) U-0 — U-0 — U-0 — R/W-0 TIECS1 (2,3) R/W-0 TIECS0(2,3) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(3) TCKPS1(3) TCKPS0(3) — — TCS(2,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = St
PIC24FJ128GC010 FAMILY 14.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 14.1 14.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Input Capture with Dedicated Timer” (DS39722). The information in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ128GC010 family contain seven independent input capture modules.
PIC24FJ128GC010 FAMILY 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs and the even module (ICy) provides the Most Significant 16 bits.
PIC24FJ128GC010 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ128GC010 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Uni
PIC24FJ128GC010 FAMILY 15.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Output Compare with Dedicated Timer” (DS39723). The information in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ128GC010 family all feature seven independent output compare modules.
PIC24FJ128GC010 FAMILY FIGURE 15-1: OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxCON2 OCxR and DCB<1:0> Comparator Clock Select OC Clock Sources Match Event Increment OC Output and OCxTMR Fault Logic Reset Match Event Trigger and Sync Sources OCx Pin(1) Trigger and Sync Logic Comparator Match Event OCFA/OCFB(2) OCxRS Reset OCx Interrupt Note 1: 2: 15.
PIC24FJ128GC010 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. 2. 3. 4. 5. 6. Set the OC32 bits for both registers (OCyCON2<8>) and (OCxCON2<8>). Enable the even numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2<7>), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit.
PIC24FJ128GC010 FAMILY FIGURE 15-2: OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR and DCB<1:0> Rollover/Reset OCxR and DCB<1:0> Buffers Clock Select OC Clock Sources Increment Comparator OCxTMR Reset Trigger and Sync Logic Trigger and Sync Sources Match Event Comparator OCx Pin(1) Match Event OC Output and Rollover Fault Logic OCFA/OCFB(2) M
PIC24FJ128GC010 FAMILY 15.3.2 PWM DUTY CYCLE • If OCxR, OCxRS and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). • If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete).
PIC24FJ128GC010 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2(2) ENFLT1(2) bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0(2) OCFLT2(2,3) OCFLT1(2,4) OCFLT0(2,4) TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n =
PIC24FJ128GC010 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 4 OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or by software 0 = TRIGSTAT is only cleared by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM mode on
PIC24FJ128GC010 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’
PIC24FJ128GC010 FAMILY REGISTER 15-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = OCTRIG1 External Input 11101 = OCTRIG2 External Input 11100 = CTMU(2) 11011 = Pipeline A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 8(2) 10110 = Input Capture 7(2) 10101 = Input Capture 6(2) 10100 = Input Capture 5(2) 10011 = Input Capture 4(2) 10010 = Inpu
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 236 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 16.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Serial Peripheral Interface (SPI)” (DS39699). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ128GC010 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ128GC010 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN(1) — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0, HSC R/C-0, HS R-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’
PIC24FJ128GC010 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FJ128GC010 FAMILY REGISTER 16-2: U-0 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — — U-0 — R/W-0 DISSCK (1) R/W-0 (2) DISSDO R/W-0 R/W-0 R/W-0 MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 (4) SSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0
PIC24FJ128GC010 FAMILY REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 11.
PIC24FJ128GC010 FAMILY REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled 0 = Framed SPIx support is disable
PIC24FJ128GC010 FAMILY FIGURE 16-3: SPIx MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 2 (SPI Slave) Processor 1 (SPI Master) SDOx SDIx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB)(2) SDIx Shift Register (SPIxSR) SDOx LSb MSb Shift Register (SPIxSR)(2) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF)(2) LSb Serial Transmit Buffer (SPIxTXB)(2) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 MSTEN
PIC24FJ128GC010 FAMILY FIGURE 16-5: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Master, Frame Master) Processor 2 SDOx SDIx SDIx SCKx SSx FIGURE 16-6: SDOx Serial Clock Frame Sync Pulse SCKx SSx SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 16-7: Processor 2 Serial Clock Frame Sync Pulse SCKx SSx SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM Processor 2 PIC24F (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx S
PIC24FJ128GC010 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED(1) FSCK = Note 1: TABLE 16-1: FCY Primary Prescaler x Secondary Prescaler Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 248 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 17.0 Note: INTER-INTEGRATED CIRCUIT™ (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Inter-Integrated Circuit™ (I2C™)” (DS39702). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Match Detect Address Match Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS30009312B-page 250 2012-2013 Microchip
PIC24FJ128GC010 FAMILY 17.2 Setting Baud Rate When Operating as a Bus Master 17.3 The I2CxMSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond, whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses, ‘0000000’ and ‘0100000’.
PIC24FJ128GC010 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
PIC24FJ128GC010 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24FJ128GC010 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV DAC P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24FJ128GC010 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 256 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “UART” (DS39708). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY 18.1 UARTx Baud Rate Generator (BRG) The UARTx module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 shows the formula for computation of the baud rate with BRGH = 0.
PIC24FJ128GC010 FAMILY 18.2 1. 2. 3. 4. 5. 6. Set up the UARTx: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UARTx. Set the UTXEN bit (causes a transmit interrupt, two cycles after being set). Write a data byte to the lower byte of the UxTXREG word.
PIC24FJ128GC010 FAMILY REGISTER 18-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) UARTEN — R/W-0 USIDL R/W-0 (2) IREN R/W-0 U-0 R/W-0 R/W-0 RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
PIC24FJ128GC010 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Se
PIC24FJ128GC010 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n
PIC24FJ128GC010 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 264 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 19.0 Note: UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “USB On-The-Go (OTG)” (DS39721). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY FIGURE 19-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up Host Pull-Down 48 MHz USB Clock D+(1) Registers and Control Interface Transceiver VUSB3V3(2) Transceiver Power 3.
PIC24FJ128GC010 FAMILY 19.1 Hardware Configuration 19.1.1 19.1.1.1 DEVICE MODE D+ Pull-up Resistor PIC24FJ128GC010 family devices have a built-in 1.5 k resistor on the D+ line that is available when the microcontroller is operating in Device mode. This is used to signal an external host that the device is operating in Full-Speed Device mode. It is engaged by setting the USBEN bit (U1CON<0>) and powering up the USB module (USBPWR = 1).
PIC24FJ128GC010 FAMILY 19.1.2 HOST AND OTG MODES 19.1.2.1 19.1.2.2 D+ and D- Pull-Down Resistors PIC24FJ128GC010 family devices have a built-in 15 k pull-down resistor on the D+ and D- lines. These are used in tandem to signal to the bus that the microcontroller is operating in Host mode. They are engaged by setting the HOSTEN bit (U1CON<3>). If the OTGEN bit (U1OTGCON<2>) is set, then these pull-downs are enabled by setting the DPPULDWN and DMPULDWN bits (U1OTGCON<5:4>).
PIC24FJ128GC010 FAMILY 19.1.3 USING AN EXTERNAL INTERFACE Some applications may require the USB interface to be isolated from the rest of the system. PIC24FJ128GC010 family devices include a complete interface to communicate with and control an external USB transceiver, including the control of data line pull-ups and pull-downs. The VBUS voltage generation control circuit can also be configured for different VBUS generation topologies. Refer to the “PIC24F Family Reference Manual”, Section 27.
PIC24FJ128GC010 FAMILY 19.2 USB Buffer Descriptors and the BDT Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available 512-byte, aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT and sets the location of the BDT in RAM.
PIC24FJ128GC010 FAMILY BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. Table 19-2 provides the mapping of BDs to endpoints. This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This, theoretically, means that the BDs for disabled endpoints could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented. 19.2.
PIC24FJ128GC010 FAMILY REGISTER 19-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC UOWN DTS PID3 PID2 PID1 PID0 BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit
PIC24FJ128GC010 FAMILY REGISTER 19-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x r-0 r-0 R/W-x R/W-x R/W-x, HSC R/W-x, HSC UOWN DTS(1) r r DTSEN BSTALL BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Un
PIC24FJ128GC010 FAMILY 19.3 An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. Unlike the device-level interrupt flags in the IFSx registers, USB interrupt flags in the U1IR registers can only be cleared by writing a ‘1’ to the bit position. USB Interrupts The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Figure 19-8 shows the interrupt logic for the USB module.
PIC24FJ128GC010 FAMILY 19.3.1 CLEARING USB OTG INTERRUPTS Note: Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in software by writing a ‘1’ to their locations (i.e., performing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., a BCLR instruction) has no effect.
PIC24FJ128GC010 FAMILY 19.4.2 1. 2. 3. 4. Attach to a USB host and enumerate as described in Chapter 9 of the “USB 2.0 Specification”. Create a data buffer and populate it with the data to send to the host. In the appropriate (even or odd) TX BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer.
PIC24FJ128GC010 FAMILY 19.5.2 1. 2. 3. 4. 5. 6. 7. COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE Follow the procedure described in Section 19.5.1 “Enable Host Mode and Discover a Connected Device” to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the “USB 2.
PIC24FJ128GC010 FAMILY 19.5.3 1. 2. 3. 4. 5. 6. 7. SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE Follow the procedure described in Section 19.5.1 “Enable Host Mode and Discover a Connected Device” and Section 19.5.2 “Complete a Control Transaction to a Connected Device” to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD (U1EP0<7>) bit.
PIC24FJ128GC010 FAMILY 19.6.2 HOST NEGOTIATION PROTOCOL (HNP) In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the “On-The-Go Supplement” to the “USB 2.0 Specification” for more information regarding HNP. HNP may only be initiated at full speed.
PIC24FJ128GC010 FAMILY 19.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 19-1 and Register 19-2, are shown separately in Section 19.2 “USB Buffer Descriptors and the BDT”.
PIC24FJ128GC010 FAMILY 19.7.
PIC24FJ128GC010 FAMILY REGISTER 19-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 DPPULUP R/W-0 R/W-0 DMPULUP DPPULDWN(1) DMPULDWN(1) r-0 R/W-0 r-0 R/W-0 r OTGEN(1) r VBUSDIS(1) bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’
PIC24FJ128GC010 FAMILY REGISTER 19-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC U-0 U-0 R/W-0 U-0 U-0 R/W-0, HC R/W-0 UACTPND — — USLPGRD — — USUSPND USBPWR bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unim
PIC24FJ128GC010 FAMILY REGISTER 19-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0 ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI(1) — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read
PIC24FJ128GC010 FAMILY REGISTER 19-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as
PIC24FJ128GC010 FAMILY REGISTER 19-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Un
PIC24FJ128GC010 FAMILY REGISTER 19-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN(1) ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB
PIC24FJ128GC010 FAMILY REGISTER 19-11: U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 CNT<7:0>: Start-of-Fra
PIC24FJ128GC010 FAMILY REGISTER 19-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 UTEYE UOEMON(1) — USBSIDL — — PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UTEYE: USB Eye Pattern Test Enable bit 1
PIC24FJ128GC010 FAMILY REGISTER 19-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — — UVCMPSEL PUVBUS EXTI2CEN — UVCMPDIS(1) UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 UVCMPSEL: VBUS Comparator E
PIC24FJ128GC010 FAMILY 19.7.
PIC24FJ128GC010 FAMILY REGISTER 19-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interru
PIC24FJ128GC010 FAMILY REGISTER 19-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to Clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
PIC24FJ128GC010 FAMILY REGISTER 19-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to Clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
PIC24FJ128GC010 FAMILY REGISTER 19-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 STALLIE ATTACHIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESUMEIE IDLEIE TRNIE SOFIE UERRIE R/W-0 URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as
PIC24FJ128GC010 FAMILY REGISTER 19-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF EOFEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to Clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FJ128GC010 FAMILY REGISTER 19-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE EOFEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enab
PIC24FJ128GC010 FAMILY 19.7.
PIC24FJ128GC010 FAMILY 20.0 The modulated output signal is generated by performing a logical AND operation of both the carrier and modulator signals and then it is provided to the MDOUT pin. Using this method, the DSM can generate the following types of key modulation schemes: DATA SIGNAL MODULATOR Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ128GC010 FAMILY REGISTER 20-1: MDCON: DATA SIGNAL MODULATOR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 MDEN — MSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 — MDOE MDSLR MDOPOL — — — MDBIT(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 MDEN: DSM Module Enable bit 1 = DSM module is enabled and mixing input signals 0 = D
PIC24FJ128GC010 FAMILY REGISTER 20-2: MDSRC: DATA SIGNAL MODULATOR SOURCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x SODIS(1) — — — MS3(2) MS2(2) MS1(2) MS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SODIS: DSM Modulation
PIC24FJ128GC010 FAMILY REGISTER 20-3: MDCAR: DATA SIGNAL MODULATOR CARRIER CONTROL REGISTER R/W-x R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CHODIS CHPOL CHSYNC — CH3(1) CH2(1) CH1(1) CH0(1) bit 15 bit 8 R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CLODIS CLPOL CLSYNC — CL3(1) CL2(1) CL1(1) CL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FJ128GC010 FAMILY 21.0 Note: ENHANCED PARALLEL MASTER PORT (EPMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Enhanced Parallel Master Port (EPMP)” (DS39730). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY TABLE 21-2: ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS Pin Name (Alternate Function) Type Description PMA<22:16> O Address Bus bits<22:16> PMA<15> (PMCS2) O Address Bus bit 15 I/O Data Bus bit 15 (16-bit port with multiplexed addressing) PMA<14> (PMCS1) PMA<13:8> O Chip Select 2 (alternate location) O Address Bus bit 14 I/O Data Bus bit 14 (16-bit port with multiplexed addressing) O Chip Select 1 (alternate location) O Address Bus bits<13:8> I/O Data Bus b
PIC24FJ128GC010 FAMILY REGISTER 21-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable
PIC24FJ128GC010 FAMILY REGISTER 21-1: bit 1-0 PMCON1: EPMP CONTROL REGISTER 1 (CONTINUED) IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt is generated at the end of a read/write cycle 00 = No interrupt is generated REGISTER 21-2: PMCON2: EPMP CONTROL REGISTER 2 R-0, HSC U-0 R/C-0, HS R/C-0, HS U-0
PIC24FJ128GC010 FAMILY REGISTER 21-3: PMCON3: EPMP CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE bit 15 bit 8 U-0 — R/W-0 PTEN22 (1) R/W-0 R/W-0 (1) PTEN21 PTEN20 (1) R/W-0 PTEN19 (1) R/W-0 PTEN18 (1) R/W-0 PTEN17 (1) R/W-0 PTEN16(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PTWREN:
PIC24FJ128GC010 FAMILY REGISTER 21-4: PMCON4: EPMP CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN15: PMA15
PIC24FJ128GC010 FAMILY REGISTER 21-5: PMCSxCF: EPMP CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CSDIS: Chip Select x Disable bit 1 = Disables the Chip Select x fu
PIC24FJ128GC010 FAMILY PMCSxBS: EPMP CHIP SELECT x BASE ADDRESS REGISTER(2) REGISTER 21-6: R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 bit 15 bit 8 R/W(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 BASE15 — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 BASE<23:15>: Chip Select x Base Address bi
PIC24FJ128GC010 FAMILY REGISTER 21-7: PMCSxMD: EPMP CHIP SELECT x MODE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 ACK
PIC24FJ128GC010 FAMILY REGISTER 21-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC R/W-0, HS U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC IBF IBOV — — IB3F(1) IB2F(1) IB1F(1) IB0F(1) bit 15 bit 8 R-1, HSC R/W-0, HS U-0 U-0 R-1, HSC R-1, HSC R-1, HSC R-1, HSC OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC24FJ128GC010 FAMILY REGISTER 21-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PM
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 314 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 22.
PIC24FJ128GC010 FAMILY 22.
PIC24FJ128GC010 FAMILY REGISTER 22-1: bit 2-0 LCDCON: LCD CONTROL REGISTER (CONTINUED) LMUX<2:0>: LCD Commons Select bits LMUX<2:0> Multiplex Bias 111 1/8 MUX (COM<7:0>) 1/3 110 1/7 MUX (COM<6:0>) 1/3 101 1/6 MUX (COM<5:0>) 1/3 100 1/5 MUX (COM<4:0>) 1/3 011 1/4 MUX (COM<3:0>) 1/3 010 1/3 MUX (COM<2:0>) 1/2 or 1/3 001 1/2 MUX (COM<1:0>) 1/2 or 1/3 000 Static (COM0) Static Note: For multiplex above 4 commons, COM4, COM5, COM6 and COM7 also have segment functionality.
PIC24FJ128GC010 FAMILY REGISTER 22-3: LCDPS: LCD PHASE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each f
PIC24FJ128GC010 FAMILY REGISTER 22-4: LCDSEx: LCD SEGMENT x ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+15)(1,2) SE(n+14) SE(n+13) SE(n+12) SE(n+11) SE(n+10) SE(n+9) SE(n+8) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+7) SE(n+6) SE(n+5) SE(n+4) SE(n+3) SE(n+2) SE(n+1) SE(n) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared b
PIC24FJ128GC010 FAMILY TABLE 22-1: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS Segments COM Lines 0 to 15 16 to 31 32 to 47 48 to 64 0 LCDDATA0 S00C0:S15C0 LCDDATA1 S16C0:S31C0 LCDDATA2 S32C0:S47C0 LCDDATA3 S48C0:S63C0 1 LCDDATA4 S00C1:S15C1 LCDDATA5 S16C1:S31C1 LCDDATA6 S32C1:S47C1 LCDDATA7 S48C1:S63C1 2 LCDDATA8 S00C2:S15C2 LCDDATA9 S16C2:S31C2 LCDDATA10 S32C2:S47C2 LCDDATA11 S48C2:S63C2 3 LCDDATA12 S00C3:S15C3 LCDDATA13 S16C3:S31C3 LCDDATA14 S32C3:S47C3 LCDDATA15
PIC24FJ128GC010 FAMILY REGISTER 22-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FJ128GC010 FAMILY REGISTER 22-6: bit 2-0 LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED) LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits Sets the number of 32 clock counts when the A Time Interval Power mode is active.
PIC24FJ128GC010 FAMILY 23.0 Note: • BCD format for smaller software overhead • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust • Optimized for long-term battery operation • Fractional second synchronization • Calibration to within ±2.
PIC24FJ128GC010 FAMILY 23.2 TABLE 23-2: RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 23.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR<1:0> bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 23-1).
PIC24FJ128GC010 FAMILY 23.3 Registers 23.3.
PIC24FJ128GC010 FAMILY REGISTER 23-1: bit 7-0 RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) (CONTINUED) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 127 RTC clock pulses every 15 seconds . . . 01111111 = Minimum positive adjustment; adds 1 RTC clock pulse every 15 seconds 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 1 RTC clock pulse every 15 seconds . . .
PIC24FJ128GC010 FAMILY REGISTER 23-2: R/W-0 PWCEN RTCPWC: RTCC POWER CONTROL REGISTER(1) R/W-0 PWCPOL R/W-0 PWCPRE R/W-0 PWSPRE R/W-0 RTCLK1 R/W-0 (2) RTCLK0 (2) R/W-0 R/W-0 RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWCEN: Power Control Enable bit 1 = Power control is enabled 0 = Powe
PIC24FJ128GC010 FAMILY REGISTER 23-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 ALRMEN bit 15 R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ARPT7 bit 7 R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is
PIC24FJ128GC010 FAMILY 23.3.
PIC24FJ128GC010 FAMILY WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 23-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY
PIC24FJ128GC010 FAMILY 23.3.
PIC24FJ128GC010 FAMILY REGISTER 23-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unk
PIC24FJ128GC010 FAMILY 23.4 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute.
PIC24FJ128GC010 FAMILY FIGURE 23-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: 23.
PIC24FJ128GC010 FAMILY 24.0 Note: 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR • User-programmable CRC polynomial equation, up to 32 bits • Programmable shift direction (little or big-endian) • Independent data and polynomial lengths • Configurable interrupt output • Data FIFO This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ128GC010 FAMILY 24.1 24.1.1 24.1.2 User Interface POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation.
PIC24FJ128GC010 FAMILY 24.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction the data is shifted into the engine.
PIC24FJ128GC010 FAMILY REGISTER 24-1: CRCCON1: CRC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = B
PIC24FJ128GC010 FAMILY REGISTER 24-2: CRCCON2: CRC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDT
PIC24FJ128GC010 FAMILY REGISTER 24-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X<31:16>: XOR of Polynomial Term x
PIC24FJ128GC010 FAMILY 25.0 OVERVIEW OF ADVANCED ANALOG FEATURES The defining feature of PIC24FJ128GC010 family devices is the collection of analog peripherals, designed to extend the range of PIC24F microcontrollers into high-performance analog and mixed-signal applications. All devices include a set of new advanced modules and several existing analog peripherals, plus a common voltage reference for ease of use.
PIC24FJ128GC010 FAMILY FIGURE 25-1: ANALOG BLOCK OVERVIEW CTMU 12-Bit Pipeline A/D Converter CTCMP CTMU Out CTPLS Temp Out BGBUF1 Sigma-Delta A/D Converter AVREF+ AVDD CTMU AN0 + CH0P CH1P AN15 SD A/D – CH1N CH0N + AN16 12-Bit A/D – SVDD SVSS Comparators C1IND C1INC C1INB C1INA C1 C2IND C2INC C2INB C2INA C2 BGBUF0 VBG/2 OA1OUT OA2OUT Temp AVDD AVSS AN49 AVREFAVSS 10-Bit DAC Converters C3IND C3INC C3INB C3INA DVREF+ AVDD C3 + DAC1 DAC1 + DAC2 DAC2 BGBUF0 BGBUF0 CVREF Comp
PIC24FJ128GC010 FAMILY TABLE 25-1: SHARED ANALOG PINS Analog Input Channel Op Amp Comparator Comparator Reference DAC Band Gap Other Analog AN0 — — CVREF+ DVREF+ BGBUF1 AVREF+ AN1 OA2PB — CVREF- — — AVREF- AN2 OA2NC C2INB — — — CTCMP AN3 OA2OUT C2INA — — — — AN4 OA1NA C1INB — — — — AN5 OA1OUT C1INA — — — — AN6 OA1PD — — — — — AN9 OA1NC — — — — — AN10 OA2PC — CVREF — — — AN11 OA2ND — — — — — AN13 OA2PD — — DAC2 — — AN14 OA
PIC24FJ128GC010 FAMILY REGISTER 25-1: BUFCON0: INTERNAL VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 BUFEN — BUFSIDL BUFSLP — — — — bit 15 bit 8 U-0 R/W-0 U-0 U-0 U-0 U-0 — BUFSTBY — — — — R/W-0 R/W-0 BUFREF1(1) BUFREF0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUFEN: Enable Buffer VREF Source bit 1 = Band
PIC24FJ128GC010 FAMILY REGISTER 25-2: BUFCONx: BAND GAP BUFFERS 1 AND 2 CONTROL REGISTERS R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 BUFEN — BUFSIDL BUFSLP — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 BUFOE BUFSTBY — — — — BUFREF1 BUFREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUFEN: Enable Buffer VREF Source bit 1 = Band
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 346 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 26.0 Note: 12-BIT HIGH-SPEED, PIPELINE A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Pipeline A/D Converter, refer to the “PIC24F Family Reference Manual”, “12-Bit, High-Speed Pipeline A/D Converter” (DS30686).
PIC24FJ128GC010 FAMILY 26.2 Registers The Pipeline A/D Converter uses a total of 116 registers. Of these, 75 registers control the module’s operations; the remainder are data and result buffers.
PIC24FJ128GC010 FAMILY FIGURE 26-1: 12-BIT PIPELINE A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AN0 AN1 16 AN2 AN14 AN15 AN16(1) Input Channel MUX VR- AN47(1) AN48(1) AN49(1) VR+ VINH VINL 12-Bit A/D ADRES31: ADRES0 (Result Buffer) Conversion Logic Data Formatting S/H VBG VBG/2 VBAT BGBUF0 Sample Control CTMU Temp Input MUX Control OPA1O Control Logic and Sample List Sequencing Threshold Detect and Compare Data OPA2O AVDD AVSS AVSS VREF+ VREF- VR Select AVDD BGBUF1 Note 1: VR+ V
PIC24FJ128GC010 FAMILY REGISTER 26-1: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADSLP FORM3 FORM2 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 PUMPEN ADCAL(2) — — — — — PWRLVL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Module Enable bit 1 = Module is enabled 0
PIC24FJ128GC010 FAMILY REGISTER 26-2: ADCON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1 PVCFG1 PVCFG0 — NVCFG0 — BUFORG r r bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 r r — — — — REFPUMP(1) r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: Converter Voltage Reference Config
PIC24FJ128GC010 FAMILY REGISTER 26-3: ADCON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC ADRC(1) — — — SLEN3 SLEN2 SLEN1 SLEN0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7(2) ADCS6(2) ADCS5(2) ADCS4(2) ADCS3(2) ADCS2(2) ADCS1(2) ADCS0(2) bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clea
PIC24FJ128GC010 FAMILY REGISTER 26-4: ADSTATH: A/D STATUS HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — PUMPST ADREADY ADBUSY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 PUMPST: A/D Boost Pump Status bit 1 = The A/D boost pump is a
PIC24FJ128GC010 FAMILY REGISTER 26-5: ADSTATL: A/D STATUS LOW REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SLOV bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — r ACCIF SL3IF(1) SL2IF(1) SL1IF(1) SL0IF(1) bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 SLOV: A/D
PIC24FJ128GC010 FAMILY REGISTER 26-6: ADLnCONH: A/D SAMPLE LIST n CONTROL HIGH REGISTER (n = 0 to 3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASEN SLINT1 SLINT0 WM1 WM0 CM2 CM1 CM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN r MULCHEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit i
PIC24FJ128GC010 FAMILY REGISTER 26-6: bit 4-0 ADLnCONH: A/D SAMPLE LIST n CONTROL HIGH REGISTER (n = 0 to 3) (CONTINUED) SAMC<4:0>: Sample/Hold Capacitor Charge Time (Acquisition Time) bits 11111 = 31 TAD 11110 = 30 TAD ··· 00001 = 1 TAD 00000 = 0.5 TAD DS30009312B-page 356 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY REGISTER 26-7: R/W-0 ADLnCONL: A/D SAMPLE LIST n CONTROL LOW REGISTER (n = 0 to 3) R/W-0 (1) SLEN SAMP R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SLENCLR SLTSRC4 SLTSRC3 SLTSRC2 SLTSRC1 SLTSRC0 bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 THSRC — — SLSIZE4 SLSIZE3 SLSIZE2 SLSIZE1 SLSIZE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
PIC24FJ128GC010 FAMILY REGISTER 26-7: bit 4-0 Note 1: ADLnCONL: A/D SAMPLE LIST n CONTROL LOW REGISTER (n = 0 to 3) (CONTINUED) SLSIZE<4:0>: Sample List Size Select bits Number of ADTBLn Registers (+ 1) Associated with this Sample List: 11111 = 32 ADTBLn registers associated with this sample list 11110 = 31 ADTBLn registers associated with this sample list ··· 00010 = 3 ADTBLn registers associated with this sample list 00001 = 2 ADTBLn registers associated with this sample list 00000 = 1 ADTBLn register
PIC24FJ128GC010 FAMILY REGISTER 26-8: ADLnSTAT: A/D SAMPLE LIST n STATUS REGISTER (n = 0 to 3) R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ADTACT LBUSY — — — — — — bit 15 bit 8 R-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 ADTDLY — ADLIF(1) — — — — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADTACT: A/D Trigger Event Active bi
PIC24FJ128GC010 FAMILY REGISTER 26-9: ADLnPTR: A/D SAMPLE LIST n POINTER REGISTER (n = 0 to 3) U-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 — ADNEXT6 ADNEXT5 ADNEXT4 ADNEXT3 ADNEXT2 ADNEXT1 ADNEXT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x =
PIC24FJ128GC010 FAMILY TABLE 26-1: ADCH<6:0> CHANNEL ENTRY SELECT VALUES FOR ADCH<6:0> Single-Ended (DIFF = 0) AIN+(1) Differential (DIFF = 1) AIN- AIN+(1) ADCH<6:0> AIN-(1) Single-Ended (DIFF = 0) Differential (DIFF = 1) AIN+(1) AIN- AIN+(1) AIN- 1111111(2) VREF- VREF- VREF- VREF- 0100001 AN33 VREF- AN33 AN14 1111110(3) VREF- VREF+ VREF- VREF+ 0100000 AN32 VREF- AN32 AN14 1111101(4) VREF+ VREF- VREF+ VREF- 0011111 AN31 VREF- AN31 AN14 1111100(2) VREF+ VREF+ VRE
PIC24FJ128GC010 FAMILY REGISTER 26-11: ACCONH: A/D ACCUMULATOR CONTROL HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0, HC R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ACEN(1) ACIE — — — — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACEN: Accumulator E
PIC24FJ128GC010 FAMILY REGISTER 26-13: ADCHITH: A/D MATCH HIT HIGH REGISTER R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS CHH31 CHH30 CHH29 CHH28 CHH27 CHH26 CHH25 CHH24 bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS CHH23 CHH22 CHH21 CHH20 CHH19 CHH18 CHH17 CHH16 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value
PIC24FJ128GC010 FAMILY REGISTER 26-15: ADTHnH: A/D SAMPLE TABLE n THRESHOLD VALUE HIGH REGISTER (n = 0 to 3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown TH<15:0
PIC24FJ128GC010 FAMILY REGISTER 26-17: ADLnMSEL3: A/D SAMPLE LIST n MULTI-CHANNEL SELECT REGISTER 3 (n = 0 to 3) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — MSEL49 MSEL48 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1-0 MSEL<49:48>: A/D Chann
PIC24FJ128GC010 FAMILY REGISTER 26-19: ADLnMSEL1: A/D SAMPLE LIST n MULTI-CHANNEL SELECT REGISTER 1 (n = 0 to 3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL31 MSEL30 MSEL29 MSEL28 MSEL27 MSEL26 MSEL25 MSEL24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL23 MSEL22 MSEL21 MSEL20 MSEL19 MSEL18 MSEL17 MSEL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is
PIC24FJ128GC010 FAMILY FIGURE 26-2: 12-BIT A/D CONVERTER SINGLE-ENDED ANALOG INPUT MODEL RIC 250 Rs VA ANx CPIN Sampling Switch RSS ILEAKAGE 50 nA typ. CHOLD = 2 pF VSS Legend: CIN = Pin Capacitance + Channel MUX Capacitance(2) VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note 1: The CIN value depends on the device package and is not tested.
PIC24FJ128GC010 FAMILY FIGURE 26-3: 12-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0010 0000 0011 (2051) 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) DS30009312B-page 368 (VINH – VINL) VR+ 4096 4095 * (VR+ – VR-) VR- + 4096 VR-+ 2048 * (VR+ – VR-) 4096 VR+ – VR- Voltage Level VR- + 0 VR- 0000 0000 0000 (0) 2012-2013 Microchip
PIC24FJ128GC010 FAMILY 27.0 cantly exceed that of conventional 10-bit or 12-bit SAR-based A/Ds. A block diagram of the 16-bit Sigma-Delta A/D is shown in Figure 27-1. 16-BIT SIGMA-DELTA ANALOG-TO-DIGITAL (A/D) CONVERTER Key features include: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “16-Bit Sigma-Delta A/D Converter” (DS30687).
PIC24FJ128GC010 FAMILY 27.1 Important Differences Compared to Conventional A/Ds In principle, the Sigma-Delta A/D Converter does what most other A/Ds do: it samples an analog input voltage and generates a digital output code representing the analog voltage. There are, however, a number of differences when comparing a Sigma-Delta Converter to conventional A/D Converters, such as the Successive Approximation Register (SAR) design that is popular on many of today’s microcontrollers.
PIC24FJ128GC010 FAMILY REGISTER 27-1: SD1CON1: S/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0 SDON — SDSIDL SDRST r SDGAIN2 SDGAIN1 SDGAIN0 bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 DITHER1 DITHER0 — VOSCAL — SDREFN SDREFP PWRLVL bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SDON: S/D Modul
PIC24FJ128GC010 FAMILY REGISTER 27-2: SD1CON2: S/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 CHOP1 CHOP0 SDINT1 SDINT0 — — SDWM1 SDWM0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 HS/C-0 — — — RNDRES1 RNDRES0 — — SDRDY bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 CHOP
PIC24FJ128GC010 FAMILY REGISTER 27-3: SD1CON3: S/D CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDDIV2(1) SDDIV1(1) SDDIV0(1) SDOSR2 SDOSR1 SDOSR0 SDCS1 SDCS0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — SDCH2 SDCH1 SDCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 SDDIV<2:0>: S/D Input Clock Divi
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 374 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 28.0 Note: The DAC generates an analog output voltage based on the digital input code, according to the formula: 10-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) VDAC = This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “10-Bit Digital-to-Analog Converter (DAC)” (DS39615).
PIC24FJ128GC010 FAMILY REGISTER 28-1: DACxCON: DACx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 DACEN — DACSIDL DACSLP DACFM — — DACTRIG bit 15 bit 8 U-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DACTSEL4 DACTSEL3 DACTSEL2 DACTSEL1 DACTSEL0 DACREF1 DACREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DACEN: DAC Enable bit
PIC24FJ128GC010 FAMILY 29.0 The two op amps are functionally identical; the block diagram for a single amplifier is shown in Figure 29-1. Each op amp has these features: DUAL OPERATIONAL AMPLIFIER MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Operational Amplifier (Op Amp)” (DS30505).
PIC24FJ128GC010 FAMILY REGISTER 29-1: AMPxCON: OP AMP x CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-x R/W-0 AMPEN — AMPSIDL AMPSLP INTPOL1 INTPOL0 CMOUT CMPSEL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPDSEL AMPOE NINSEL2 NINSEL1 NINSEL0 PINSEL2 PINSEL1 PINSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AMPEN:
PIC24FJ128GC010 FAMILY REGISTER 29-1: AMPxCON: OP AMP x CONTROL REGISTER bit 5-3 NINSEL<2:0>: Op Amp Inverting Input Select bits 111 = Reserved; do not use 110 = Op Amp output (voltage follower configuration) 101 = OAxNE 100 = OAxND 011 = OAxNC 010 = OAxNB 001 = OAxNA 000 = VSS bit 2-0 PINSEL<2:0>: Op Amp Non-Inverting Input Select bits 111 = Reserved; do not use 110 = Connected between CTMU output and Pipeline A/D 101 = OAxPE 100 = OAxPD 011 = OAxPC 010 = OAxPB 001 = OAxPA 000 = VSS 2012-2013 Micro
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 380 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 30.0 voltage reference input from one of the internal band gap references or the comparator voltage reference generator (VBG, VBG/2, VBG/6 and CVREF). TRIPLE COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Scalable Comparator Module” (DS39734).
PIC24FJ128GC010 FAMILY FIGURE 30-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN = 0, CREF = x, CCH<1:0> = xx COE VINVIN+ Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CEN = 1, CCH<1:0> = 00, CVREFM<1:0> = xx CEN = 1, CCH<1:0> = 01, CVREFM<1:0> = xx CXINB CXINA COE VINVIN+ CXINC Cx CxOUT Pin CXINA COE VINVIN+ Cx CxOUT Pin Comparator CxIND > CxINA Compare Comparator VBG > CxINA Compare CEN = 1, CCH<1:0> = 10, CV
PIC24FJ128GC010 FAMILY FIGURE 30-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN = 1, CCH<1:0> = 00, CVREFM<1:0> = xx CEN = 1, CCH<1:0> = 01, CVREFM<1:0> = xx CXINB CVREF COE VINVIN+ Cx CxOUT Pin COE VIN- CXINC VIN+ CVREF Cx CxOUT Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 10, CVREFM<1:0> = xx CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 00 CXIND CVREF COE VI
PIC24FJ128GC010 FAMILY REGISTER 30-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ =
PIC24FJ128GC010 FAMILY REGISTER 30-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 386 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 31.0 Note: COMPARATOR VOLTAGE REFERENCE 31.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Dual Comparator Module” (DS39710). The information in this data sheet supersedes the information in the FRM.
PIC24FJ128GC010 FAMILY REGISTER 31-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0
PIC24FJ128GC010 FAMILY 32.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, “Charge Time Measurement Unit (CTMU) with Threshold Detect” (DS39743).
PIC24FJ128GC010 FAMILY FIGURE 32-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP 32.2 RPR Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s Internal Capacitor (CAD) and a precision resistor for current calibration.
PIC24FJ128GC010 FAMILY FIGURE 32-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDX EDG1 CTEDX EDG2 Current Source Output Pulse A/D Converter ANx CAD RPR FIGURE 32-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDX EDG1 CTMU CTPLS Current Source Comparator C2INB – CDELAY CVREF 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY REGISTER 32-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimp
PIC24FJ128GC010 FAMILY REGISTER 32-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24FJ128GC010 FAMILY REGISTER 32-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented Do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is IC1 1000 = Edge 2 source is CTED13 0111 = Edge 2 source is CTED12 0110 = Edge 2 source is CTED11(1) 0101 = Edge 2 source is CTED10(1)
PIC24FJ128GC010 FAMILY REGISTER 32-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change f
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 396 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 33.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ128GC010 FAMILY REGISTER 33-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — LSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power En
PIC24FJ128GC010 FAMILY 34.0 Note: 34.1.1 SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”. The information in this data sheet supersedes the information in the FRMs. In PIC24FJ128GC010 family devices, the configuration bytes are implemented as volatile memory.
PIC24FJ128GC010 FAMILY REGISTER 34-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r JTAGEN GCP GWRP DEBUG LPCFG ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN1 FWDTEN0 WINDIS FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit PO = Program Once bit R = Readable bit W = Writable bit U = Uni
PIC24FJ128GC010 FAMILY REGISTER 34-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY REGISTER 34-2: CW2: FLASH CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 IESO VBTBOR R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WDTCMX ALTCVREF(1) ALTADREF(1) FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-0 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN WDTCLK1 WDTCLK0 r POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit PO = Program Once bit R = Readable bit W
PIC24FJ128GC010 FAMILY REGISTER 34-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 5 OSCIOFCN: OSCO Pin Configuration bit If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15.
PIC24FJ128GC010 FAMILY REGISTER 34-3: CW3: FLASH CONFIGURATION WORD 3 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 R/PO-1 WPEND WPCFG WPDIS BOREN r WDTWIN1 WDTWIN0 SOSCSEL bit 15 bit 8 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r WPFP6(3) WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimpl
PIC24FJ128GC010 FAMILY REGISTER 34-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) WPFP<6:0>: Write-Protected Code Segment Boundary Page bits(3) Designates the 512 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary.
PIC24FJ128GC010 FAMILY REGISTER 34-4: CW4: FLASH CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IOL1WAY I2C2SEL PLLDIV3 PLLDIV2 PLLDIV1 PLLDIV0 RTCBAT DSSWEN bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DSWDTEN DSBOREN DSWDTOSC DSWDPS4 DSWDPS3 DSWDPS2 DSWDPS1 DSWDPS0 bit 7 bit 0 Legend: PO = Program Once bit R = Readable bit W = Writab
PIC24FJ128GC010 FAMILY REGISTER 34-4: CW4: FLASH CONFIGURATION WORD 4 (CONTINUED) bit 6 DSBOREN: Deep Sleep Brown-out Reset Enable bit 1 = BOR is enabled in Deep Sleep mode 0 = BOR is disabled in Deep Sleep mode (remains active in other Sleep modes) bit 5 DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit 1 = Clock source is LPRC 0 = Clock source is SOSC bit 4-0 DSWDPS<4:0>: Deep Sleep Watchdog Timer Postscaler Select bits 11111 = 1:68,719,476,736 (25.7 days) 11110 = 1:34,359,738,368(12.
PIC24FJ128GC010 FAMILY REGISTER 34-5: DEVID: DEVICE ID REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 0100 1000 = PIC24FJ128GC010 family bit
PIC24FJ128GC010 FAMILY 34.2 On-Chip Voltage Regulator All PIC24FJ128GC010 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GC010 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. This regulator is always enabled. It provides a constant voltage (1.
PIC24FJ128GC010 FAMILY 34.3 Watchdog Timer (WDT) For PIC24FJ128GC010 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24FJ128GC010 FAMILY 34.4 Program Verification and Code Protection PIC24FJ128GC010 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 34.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ128GC010 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS).
PIC24FJ128GC010 FAMILY 34.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value.
PIC24FJ128GC010 FAMILY 35.
PIC24FJ128GC010 FAMILY 35.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC24FJ128GC010 FAMILY 35.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ128GC010 FAMILY 35.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC24FJ128GC010 FAMILY 36.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F Instruction Set Architecture (ISA) and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FJ128GC010 FAMILY TABLE 36-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit Bit Selection field (used in word addressed instructions) {0...
PIC24FJ128GC010 FAMILY TABLE 36-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FJ128GC010 FAMILY TABLE 36-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FJ128GC010 FAMILY TABLE 36-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 W
PIC24FJ128GC010 FAMILY TABLE 36-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 No
PIC24FJ128GC010 FAMILY TABLE 36-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 424 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 37.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ128GC010 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GC010 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FJ128GC010 FAMILY 37.1 DC Characteristics FIGURE 37-1: PIC24FJ128GC010 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V Voltage (VDD) PIC24FJXXXGC0XX (Note 1) (Note 1) 32 MHz Frequency Note 1: TABLE 37-1: Lower recommended operating boundary is 2.0V or VBOR (when BOR is enabled). For best analog performance, operation above 2.2V is suggested, but not required.
PIC24FJ128GC010 FAMILY TABLE 37-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Min Typ Max Units V Conditions Operating Voltage DC10 VDD Supply Voltage 2.0 — 3.6 VBOR — 3.
PIC24FJ128GC010 FAMILY TABLE 37-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Operating Temperature VDD Conditions Operating Current (IDD)(2) DC19 DC20 0.20 0.28 mA -40°C to +85°C 2.0V 0.21 0.28 mA -40°C to +85°C 3.3V 0.38 0.52 mA -40°C to +85°C 2.0V 0.39 0.52 mA -40°C to +85°C 3.3V 1.5 2.
PIC24FJ128GC010 FAMILY TABLE 37-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter Typical(1) No. Max Units Operating Temperature Conditions VDD Power-Down Current (IPD) DC60 DC61 DC70 DC74 Note 1: 2: 3: 4: 2.9 — A -40°C 4.3 17 A +25°C 8.3 — A +60°C 20 27.5 A +85°C 2.9 — A -40°C 4.3 18 A +25°C 8.4 — A +60°C 20.
PIC24FJ128GC010 FAMILY TABLE 37-7: DC CHARACTERISTICS: CURRENT (BOR, WDT, DSBOR, DSWDT, LCD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Operating Temperature VDD Conditions Incremental Current Brown-out Reset (BOR)(2) DC25 3.1 5.0 A -40°C to +85°C 2.0V 4.3 6.0 A -40°C to +85°C 3.3V BOR(2) Incremental Current Watchdog Timer (WDT)(2) DC71 0.8 1.
PIC24FJ128GC010 FAMILY TABLE 37-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.
PIC24FJ128GC010 FAMILY TABLE 37-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VOL DO10 OSCO/CLKO VOH DO20 Typ(1) Max Units Conditions — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V 3.0 — — V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.
PIC24FJ128GC010 FAMILY TABLE 37-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristics Min Typ Max Units DVR10 VBG Internal Band Gap Reference — 1.2 — V DVR11 TBG Band Gap Reference Start-up Time — 1 — ms Comments DVR20 VRGOUT Regulator Output Voltage — 1.8 — V VDD > 2.0V DVR21 CEFC External Filter Capacitor Value 4.7 10 — F Series Resistance < 3 recommended; < 5 required.
PIC24FJ128GC010 FAMILY TABLE 37-13: VBAT OPERATING VOLTAGE SPECIFICATIONS Param Symbol No. Characteristic Typ Max Units 1.6 — 3.6 V Battery connected to the VBAT pin, VBTBOR = 0 VBATBOR — 3.6 V Battery connected to the VBAT pin, VBTBOR = 1 1.6 — 3.
PIC24FJ128GC010 FAMILY TABLE 37-16: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. DC18 VHLVD DC101 VTHL Note 1: Characteristic HLVD Voltage on VDD Transition HLVD Voltage on HLVDIN Pin Transition Min Typ Max Units HLVDL<3:0> = 0100(1) 3.45 — 3.73 V HLVDL<3:0> = 0101 3.30 — 3.57 V HLVDL<3:0> = 0110 3.00 — 3.25 V HLVDL<3:0> = 0111 2.80 — 3.03 V HLVDL<3:0> = 1000 2.67 — 2.92 V HLVDL<3:0> = 1001 2.
PIC24FJ128GC010 FAMILY TABLE 37-19: OPERATIONAL AMPLIFIER SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C, 2.0V < (A)VDD < 3.6V Param No. Sym Characteristics Min Typ Max Units Comments Op Amp Mode Specifications CM20a SR Slew Rate CM20B — 1.2 — V/µs SPDSEL = 1 — 0.4 — V/µs SPDSEL = 0 CM23 GBW Gain Bandwidth Product — 2.5 — MHz SPDSEL = 1 — 0.
PIC24FJ128GC010 FAMILY 37.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ128GC010 family AC characteristics and timing parameters. TABLE 37-20: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Operating voltage VDD range as described in Section 37.1 “DC Characteristics”.
PIC24FJ128GC010 FAMILY FIGURE 37-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OS30 OS30 Q1 Q2 Q3 OSCI OS20 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 37-22: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC mode) DC 1.
PIC24FJ128GC010 FAMILY TABLE 37-23: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic OS50 FPLLI PLL Input Frequency Range(1) OS52 TLOCK PLL Start-up Time (Lock Time) OS53 DCLK CLKO Stability (Jitter) Note 1: Min Typ Max Units 1.97 4 4.04 MHz — — 128 s -0.25 — 0.
PIC24FJ128GC010 FAMILY FIGURE 37-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 37-2 for load conditions. TABLE 37-26: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.
PIC24FJ128GC010 FAMILY TABLE 37-27: RESET AND BROWN-OUT RESET REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.0V to 3.
PIC24FJ128GC010 FAMILY TABLE 37-28: 12-BIT PIPELINE A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Min. Typ Max. Units — Lesser of: (VDD + 0.3) or 3.6 V Conditions Device Supply AD01 AVDD Module VDD Supply Greater of: (VDD – 0.3) or 2.0 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V AD03 IQADC1 AVDD Current — 0.
PIC24FJ128GC010 FAMILY FIGURE 37-5: 12-Bit A/D DNL, 10 MS/S, AVDD = 3.0V, TYPICAL 0.8 0.6 DNL (LSBs) 0.4 0.2 L0 N D -0.2 -0.4 -0.6 -0.8 0 512 1024 1536 2048 2560 3072 3584 4095 4096 3072 3584 4095 4096 Code Word FIGURE 37-6: 12-Bit A/D INL, 10 MS/S, AVDD = 3.0V, TYPICAL 3 2.5 2 INL (LSBs) 1.5 1 0.5 0 -0.5 -1 -1.5 0 512 1024 1536 2048 2560 Code Word 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY TABLE 37-29: 12-BIT PIPELINE A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No. Sym Characteristic Min. Typ Max. Units 1000 ns Conditions Clock Parameters A/D Clock Period 100 — AD50 TAD AD55 tCONV Single Conversion Latency — 9 — TAD AD56 FCNV — — 10 Msps AD57 tSAMP Sample Time 0.
PIC24FJ128GC010 FAMILY TABLE 37-31: 16-BIT SIGMA-DELTA A/D CONVERTER SPECIFICATIONS AC Characteristics Param No. Operating Conditions: -40°C < TA < +85°C, 2.0V < SVDD < 3.
PIC24FJ128GC010 FAMILY FIGURE 37-7: 16-Bit S/D A/D DNL, SVDD = 3.0V, TYPICAL 1 0.8 0.6 0.4 DNL (LSBs) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -32768 FIGURE 37-8: -22768 -12768 -2768 7232 Code Word 17232 27232 16-Bit S/D A/D INL, SVDD = 3.0V, TYPICAL 6 4 2 0 INL (LSBs) -2 -4 -6 -8 -10 -12 -32768 DS30009312B-page 446 -22768 -12768 -2768 7232 Code Word 17232 27232 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 38.0 PACKAGING INFORMATION 38.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN e3 * Note: PIC24FJ128 GC006-I/MR e3 1350017 Example PIC24FJ128 GC006-I/ PT e3 1320017 100-Lead TQFP (12x12x1 mm) Legend: XX...
PIC24FJ128GC010 FAMILY 38.2 Package Marking Information (Continued) 121-BGA (10x10x1.1 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS30009312B-page 448 Example PIC24FJ128 GC010-I/BG e3 1320017 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 38.3 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009312B-page 450 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 α A φ c A2 β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW
PIC24FJ128GC010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )
PIC24FJ128GC010 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY DS30009312B-page 456 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY DS30009312B-page 458 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY APPENDIX A: REVISION HISTORY Revision A (July 2012) Original data sheet for the PIC24FJ128GC010 family of devices. Revision B (May 2013) Changes descriptive title on Page 1 to “16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology”. Adds CoreMark® rating to the “High-Performance CPU” section on Page 2. Removes all references to JTAG device programming throughout the document.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 460 2012-2013 Microchip Technology Inc.
PIC24FJ128GC010 FAMILY INDEX LCD Controller.......................................................... 315 MCLR Pin Connections Example ............................... 34 On-Chip Regulator Connections............................... 409 Output Compare x (16-Bit Mode) ............................. 228 Output Compare x (Double-Buffered, 16-Bit PWM Mode) ........................................... 230 PCI24FJ128GC010 Family (General) ........................ 18 PIC24F CPU Core ...................................
PIC24FJ128GC010 FAMILY Code Protection ................................................................ 411 Code Segment Protection ......................................... 411 Configuration Options ....................................... 411 Configuration Protection ........................................... 412 General Segment Protection..................................... 411 Comparator Voltage Reference ........................................ 387 Configuring..........................................
PIC24FJ128GC010 FAMILY I N I/O Ports Analog Port Pins Configuration (ANSx) .................... 184 Analog/Digital Function of an I/O Pin ........................ 184 Input Change Notification (ICN) ................................ 191 Input Voltage Levels for Port/Pin Tolerated Description Input............................... 185 Open-Drain Configuration ......................................... 184 Parallel (PIO) ............................................................ 183 Peripheral Pin Select ....
PIC24FJ128GC010 FAMILY Program Verification.......................................................... 411 Pulse-Width Modulation (PWM) Mode .............................. 229 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 230 R Reader Response ............................................................. 468 Real-Time Clock and Calendar (RTCC)............................ 323 Reference Clock Output....................................................
PIC24FJ128GC010 FAMILY IEC4 (Interrupt Enable Control 4) ............................. 128 IEC5 (Interrupt Enable Control 5) ............................. 129 IEC6 (Interrupt Enable Control 6) ............................. 130 IEC7 (Interrupt Enable Control 7) ............................. 131 IFS0 (Interrupt Flag Status 0) ................................... 112 IFS1 (Interrupt Flag Status 1) ................................... 114 IFS2 (Interrupt Flag Status 2) ...................................
PIC24FJ128GC010 FAMILY U1OTGIE (USB OTG Interrupt Enable, Host Mode) ....................................................... 292 U1OTGIR (USB OTG Interrupt Status, Host Mode) ....................................................... 291 U1OTGSTAT (USB OTG Status, Host Mode) .......... 281 U1PWRC (USB Power Control) ................................ 283 U1SOF (USB OTG Start-of-Token Threshold, Host Mode) ....................................................... 288 U1STAT (USB Status) ............................
PIC24FJ128GC010 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ128GC010 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24FJ128GC010 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 128 GC0 10 T - I / PT - XXX Examples: a) PIC24FJ64GC006-I/MR: PIC24F device with Advanced Analog, LCD Controller and XLP Technology, 64-Kbyte Program Memory, 64-pin, Industrial temp., QFN package.
PIC24FJ128GC010 FAMILY NOTES: DS30009312B-page 470 2012-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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