Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 325
PIC24FV16KM204 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (February 2013)
Original data sheet for the PIC24FV16KM204 family of
devices.
Revision B (July 2013)
Updates all references to PGCx and PGDx pin functions
throughout the document to PGECx and PGEDx.
Updates Section 4.0 “Memory Organization” to
change bit 12 in the following registers to reserved (“r”
designation):
• CCP1CON1L (Table 4-8)
• CCP2CON1L (Table 4-9)
• CCP3CON1L (Table 4-10)
• CCP4CON1L (Table 4-11)
• CCP5CON1L (Table 4-12)
Updates Section 13.0 “Capture/Compare/PWM/
Timer Modules (MCCP and SCCP)”:
• Replaces bit 12 of CCPxCON1L (CCPSLP) and
its description with a reserved bit
• Removes references to asynchronous operation
in Sleep mode (and in other occurrences
throughout the document)
• Modifies Section 13.1 “Time Base Generator”
to add synchronous operation limitations; adds
Table 13-1 to list valid clock options for all
operating modes
• Removes the system clock as a time base input
option
• Removes external input sources, comparators
and CTMU as synchronization sources in
Table 13-6; clarifies that other selected sources
must be synchronous
Removes the input buffer from the band gap reference
input in Figure 20-1.
Adds BUFCON0 register description (Register 20-2) to
Section 20.0 “8-Bit Digital-to-Analog Converter
(DAC)”.
Changes references to internal band gap voltages
(V
BG, VBG/2 and BGBUF0) in Section 20.0 “8-Bit
Digital-to-Analog Converter (DAC)” and
Section 22.0 “Comparator Module” to BGBUF1.
Adds minimum V
DD conditions for VBG specification in
Table 27-15 (Internal Voltage Regulator Specifications).
Other minor typographical corrections throughout the
document.