Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 295
PIC24FV16KM204 FAMILY
FIGURE 27-19: A/D CONVERSION TIMING
TABLE 27-38: A/D CONVERSION TIMING REQUIREMENTS
(1)
AC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204)
2.0V to 5.5V (PIC24FV16KM204)
Operating temperature -40°C  T
A  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param
No.
Sym Characteristic Min. Typ Max. Units Conditions
Clock Parameters
AD50 TAD A/D Clock Period 600 — — ns TCY = 75 ns, AD1CON3 in
default state
AD51 T
RC A/D Internal RC Oscillator Period — 1.67 — µs
Conversion Rate
AD55 T
CONV Conversion Time —
—
12
14
—
—
TAD
TAD
10-bit results
12-bit results
AD56 F
CNV Throughput Rate — — 100 ksps
AD57 T
SAMP Sample Time — 1 — TAD
AD58 TACQ Acquisition Time 750 — — ns (Note 2)
AD59 T
SWC Switching Time from Convert to
Sample
——(Note 3)
AD60 T
DIS Discharge Time 12 — — TAD
Clock Parameters
AD61 T
PSS Sample Start Delay from
Setting Sample bit (SAMP)
2— 3 TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD).
3: On the following cycle of the device clock.
AD55
AD50
AD58
BCLR AD1CON1, SAMP
Q3/Q4
A/D CLK
(1)
A/D DATA
ADC1BUFx
AD1IF
SAMP
Old Data
Sampling Stopped
New Data
(Note 2)
11 10 9 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
BSET AD1CON1, SAMP
AD59