Datasheet
2013 Microchip Technology Inc. DS30003030B-page 257
PIC24FV16KM204 FAMILY
25.2 On-Chip Voltage Regulator
All of the PIC24FXXXXX family devices power their
core digital logic at a nominal 3.0V. This may create an
issue for designs that are required to operate at a
higher typical voltage, as high as 5.0V. To simplify sys-
tem design, all devices in the “FV” family incorporate an
on-chip regulator that allows the device core to run at
3.0V, while the I/O is powered by V
DD at a higher
voltage.
The regulator is always enabled and provides power to
the core from the other V
DD pins. A low-ESR capacitor
(such as ceramic) must be connected to the V
CAP pin
(Figure 25-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 27.1 “DC Characteristics”
and discussed in detail in Section 2.0 “Guidelines for
Getting Started with 16-Bit Microcontrollers”.
In all of the “F” family of devices, the regulator is
disabled. Instead, the core logic is directly powered
from V
DD. “F” devices operate at a lower range of VDD
voltage, from 1.8V-3.6V.
25.2.1 VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
For all PIC24FXXXXX devices, the on-chip regulator
provides a constant voltage of 3.0V nominal to the dig-
ital core logic. The regulator can provide this level from
a V
DD of about 3.2V, all the way up to the device’s
V
DDMAX. It does not have the capability to boost VDD
levels below 3.2V. In order to prevent “brown out” con-
ditions when the voltage drops too low for the regulator,
the regulator enters Tracking mode. In Tracking mode,
the regulator output follows V
DD with a typical voltage
drop of 150 mV.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip High/Low-Voltage Detect (HLVD) module can be
used. The HLVD trip point should be configured so that
if V
DD drops close to the minimum voltage for the oper-
ating frequency of the device, the HLVD Interrupt Flag,
HLVDIF (IFS4<8>), will occur. This can be used to
generate an interrupt and put the application into a
low-power operational mode or trigger an orderly
shutdown. Refer to Section 27.1 “DC Characteristics”
for the specifications detailing the maximum operating
speed based on the applied V
DD voltage.
FIGURE 25-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
25.2.2 VOLTAGE REGULATOR START-UP
TIME
For PIC24FXXXXX family devices, it takes a short time,
designated as T
PM, for the regulator to generate a
stable output. During this time, code execution is dis-
abled. TPM is applied every time the device resumes
operation after any power-down, including Sleep mode.
TPM is specified in Section 27.2 “AC Characteristics
and Timing Parameters”.
25.3 Watchdog Timer (WDT)
For the PIC24FXXXXX family of devices, the WDT is
driven by the LPRC Oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (T
WDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranges from
1 ms to 131 seconds can be achieved.
VDD
VCAP
VSS
PIC24FV16KM
CEFC
5.0V
(10 F typ)
Regulator Enabled:
(1)
Note 1: These are typical operating voltages. Refer to
Section 27.0 “Electrical Characteristics” for
the full operating ranges of V
DD and VDDCORE.