Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 248  2013 Microchip Technology Inc.
REGISTER 24-3: CTMUCON2L: CTMU CONTROL 2 LOW REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — —IRSTEN— DISCHS2 DISCHS1 DISCHS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 IRSTEN: CTMU Current Source Reset Enable bit
1 = Signal selected by the DISCHS<2:0> bits or the IDISSEN control bit will reset the CTMU edge
detect logic
0 = CTMU edge detect logic will not occur
bit 3 Unimplemented: Read as ‘0’
bit 2-0 DISCHS<2:0>: Discharge Source Select bits
111 = CLC2 output
110 = CLC1 output
101 = Reserved; do not use.
100 = A/D end of conversion signal
011 = SCCP5 auxiliary output
110 = MCCP2 auxiliary output
001 = MCCP1 auxiliary output
000 = No discharge source selected, use the IDISSEN bit