Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 237
PIC24FV16KM204 FAMILY
REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0
CON COE CPOL CLPWR
— — CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
EVPOL1
(2)
EVPOL0
(2)
— CREF1 CREF0 — CCH1 CCH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Comparator x Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator x Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator x Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12 CLPWR: Comparator x Low-Power Mode Select bit
1 = Comparator operates in Low-Power mode
0 = Comparator does not operate in Low-Power mode
bit 11-10 Unimplemented: Read as ‘0’
bit 9 CEVT: Comparator x Event bit
1 = Comparator event, defined by EVPOL<1:0>, has occurred; subsequent Triggers and interrupts are
disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8 COUT: Comparator x Output bit
When CPOL =
0:
1 =VIN+ > VIN-
0 =V
IN+ < VIN-
When CPOL =
1:
1 =VIN+ < VIN-
0 =V
IN+ > VIN-
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
(2)
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on the high-to-low transition of the comparator output
01 = Trigger/event/interrupt is generated on the low-to-high transition of the comparator output
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4-3 CREF<1:0>: Comparator x Reference Select bits (non-inverting input)
11 = Non-inverting input connects to the DAC2 output
10 = Non-inverting input connects to the DAC1 output
01 = Non-inverting input connects to the internal CV
REF voltage
00 = Non-inverting input connects to the CxINA pin
Note 1: BGBUF1 voltage is configured by BUFREF1<1:0> (BUFCON0<1:0>).
2: If the EVPOL<1:0> bits are set to a value other than ‘00’, the first interrupt generated will occur on any
transition of COUT. Subsequent interrupts will occur based on the EVPOLx bits setting.