Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 223
PIC24FV16KM204 FAMILY
19.2 A/D Sampling Requirements
The analog input model of the 12-bit A/D Converter is
shown in Figure 19-2. The total sampling time for the
A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy, the
Charge Holding Capacitor (C
HOLD) must be allowed to
fully charge to the voltage level on the analog input pin.
The Source Impedance (R
S), the Interconnect Imped-
ance (R
IC) and the Internal Sampling Switch Impedance
(R
SS) combine to directly affect the time required to
charge C
HOLD. The combined impedance of the analog
sources must, therefore, be small enough to fully charge
the holding capacitor within the chosen sample time. To
minimize the effects of pin leakage currents on the accu-
racy of the A/D Converter, the maximum recommended
source impedance, R
S, is 2.5 k. After the analog input
channel is selected (changed), this sampling function
must be completed prior to starting the conversion. The
internal holding capacitor will be in a discharged state
prior to each sample operation.
At least 1 T
AD time period should be allowed between
conversions for the sample time. For more details, see
Section 27.0 “Electrical Characteristics”.
EQUATION 19-1: A/D CONVERSION CLOCK
PERIOD
FIGURE 19-2: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
Note: Based on TCY = 2/FOSC; Doze mode
and PLL are disabled.
T
AD = TCY (ADCS + 1)
ADCS =
T
AD
TCY
– 1
CPIN
Rs
ANx
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
VSS
= 32 pF
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the Pin Due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample-and-Hold Capacitance (from DAC)
Various Junctions
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.
VA
RSS  3 k