Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 219
PIC24FV16KM204 FAMILY
bit 7-5 CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits
The same definitions as for CHONB<2:0>.
bit 4-0 CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits
The same definitions as for CHONA<4:0>.
REGISTER 19-5: AD1CHS: A/D SAMPLE SELECT REGISTER (CONTINUED)
Note 1: This is implemented on 44-pin devices only.
2: This is implemented on 28-pin and 44-pin devices only.
3: The band gap value used for this input is 2x or 4x the internal V
BG, which is selected when PVCFG<1:0> = 1x.
REGISTER 19-6: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHH23 CHH22 CHH21 CHH20
(2)
CHH19
(2)
CHH18 CHH17 CHH16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’.
bit 7-0 CHH<23:16>: A/D Compare Hit bits
(2)
If CM<1:0> = 11:
1 = A/D Result Buffer x has been written with data or a match has occurred
0 = A/D Result Buffer x has not been written with data
For All Other Values of CM<1:0>:
1 = A match has occurred on A/D Result Channel x
0 = No match has occurred on A/D Result Channel x
Note 1: Unimplemented channels are read as ‘0’.
2: The CHH<20:19> bits are not implemented in 20-pin devices.