Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 212  2013 Microchip Technology Inc.
19.1 A/D Control Registers
The 12-bit A/D Converter module uses up to
43 registers for its operation. All registers are mapped
in the data memory space.
19.1.1 CONTROL REGISTERS
Depending on the specific device, the module has up to
eleven control and status registers:
• AD1CON1: A/D Control Register 1
• AD1CON2: A/D Control Register 2
• AD1CON3: A/D Control Register 3
• AD1CON5: A/D Control Register 5
• AD1CHS: A/D Sample Select Register
• AD1CHITH and AD1CHITL: A/D Scan Compare
Hit Registers
• AD1CSSH and AD1CSSL: A/D Input Scan Select
Registers
• AD1CTMENH and AD1CTMENL: CTMU Enable
Registers
The AD1CON1, AD1CON2 and AD1CON3 registers
(Register 19-1, Register 19-2 and Register 19-3) control
the overall operation of the A/D module. This includes
enabling the module, configuring the conversion clock
and voltage reference sources, selecting the sampling
and conversion Triggers, and manually controlling the
sample/convert sequences. The AD1CON5 register
(Register 19-4) specifically controls features of the
Threshold Detect operation, including its function in
power-saving modes.
The AD1CHS register (Register 19-5) selects the input
channels to be connected to the S/H amplifier. It also
allows the choice of input multiplexers and the selection
of a reference source for differential sampling.
The AD1CHITH and AD1CHITL registers
(Register 19-6 and Register 19-7) are semaphore
registers used with Threshold Detect operations. The
status of individual bits, or bit pairs in some cases,
indicates if a match condition has occurred. AD1CHITL
is always implemented, whereas AD1CHITH may not
be implemented in devices with 16 or fewer channels.
The AD1CSSH/L registers (Register 19-8 and
Register 19-9) select the channels to be included for
sequential scanning.
The AD1CTMENH/L registers (Register 19-10 and
Register 19-11) select the channel(s) to be used by the
CTMU during conversions. Selecting a particular
channel allows the A/D Converter to control the CTMU
(particularly, its current source) and read its data through
that channel. AD1CTMENL is always implemented,
whereas AD1CTMENH may not be implemented in
devices with 16 or fewer channels.
19.1.2 A/D RESULT BUFFERS
The module incorporates a multi-word, dual port buffer,
called ADC1BUFx. Each of the locations is mapped
into the data memory space and is separately
addressable. The buffer locations are referred to as
ADC1BUF0 through ADC1BUFx (x = up to 17).
The A/D result buffers are both readable and writable.
When the module is active (AD1CON<15> = 1), the
buffers are read-only and store the results of A/D
conversions. When the module is inactive
(AD1CON<15> = 0), the buffers are both readable and
writable. In this state, writing to a buffer location programs
a conversion threshold for Threshold Detect operations.
Buffer contents are not cleared when the module is
deactivated with the ADON bit (AD1CON1<15>).
Conversion results and any programmed threshold
values are maintained when ADON is set or cleared.