Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 201
PIC24FV16KM204 FAMILY
bit 6-4 DS2<2:0>: Data Selection MUX 2 Signal Selection bits
111 = MCCP2 Compare Event Flag (CCP2IF)
110 = MCCP1 Compare Event Flag (CCP1IF)
101 = Digital logic low
100 = A/D end of conversion event
For CLC1:
011 = UART1 TX
010 = Comparator 1 output
001 = CLC2 output
000 = CLCINB I/O pin
For CLC2:
011 = UART2 TX
010 = Comparator 1 output
001 = CLC1 output
000 = CLCINB I/O pin
bit 3 Unimplemented: Read as ‘0’
bit 2-0 DS1<2:0>: Data Selection MUX 1 Signal Selection bits
111 = SCCP5 Compare Event Flag (CCP5IF)
110 = SCCP4 Compare Event Flag (CCP4IF)
101 = Digital logic low
100 = 8 MHz FRC clock source
011 = LPRC clock source
010 = SOSC clock source
001 = System clock (T
CY)
000 = CLCINA I/O pin
REGISTER 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED)