Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 200  2013 Microchip Technology Inc.
REGISTER 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— DS42 DS41 DS40 — DS32 DS31 DS30
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— DS22 DS21 DS20 — DS12 DS11 DS10
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 DS4<2:0>: Data Selection MUX 4 Signal Selection bits
111 = MCCP3 Compare Event Flag (CCP3IF)
110 = MCCP1 Compare Event Flag (CCP1IF)
101 = Digital logic low
100 = CTMU Trigger interrupt
For CLC1:
011 = SPI1 SDIx
010 = Comparator 3 output
001 = CLC2 output
000 = CLCINB I/O pin
For CLC2:
011 = SPI2 SDIx
010 = Comparator 3 output
001 = CLC1 output
000 = CLCINB I/O pin
bit 11 Unimplemented: Read as ‘0’
bit 10-8 DS3<2:0>: Data Selection MUX 3 Signal Selection bits
111 = MCCP3 Compare Event Flag (CCP3IF)
110 = MCCP2 Compare Event Flag (CCP2IF)
101 = Digital logic low
For CLC1:
100 = UART1 RX
011 = SPI1 SDOx
010 = Comparator 2 output
001 = CLC1 output
000 = CLCINA I/O pin
For CLC2:
100 = UART2 RX
011 = SPI2 SDOx
010 = Comparator 2 output
001 = CLC2 output
000 = CLCINA I/O pin
bit 7 Unimplemented: Read as ‘0’