Datasheet

 2013 Microchip Technology Inc. DS30003030B-page 197
PIC24FV16KM204 FAMILY
FIGURE 17-3: CLCx INPUT SOURCE SELECTION DIAGRAM
Gate 1
G1POL
Data Gate 1
G1D1T
Gate 2
Gate 3
Gate 4
Data Gate 2
Data Gate 3
Data Gate 4
G1D1N
DS1x (CLCxSEL<2:0>)
DS2x (CLCxSEL<6:4>)
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[5]
CLCIN[6]
CLCIN[7]
Data Selection
Note: All controls are undefined at power-up.
Data 1 Non-Inverted
Data 1
Data 2 Non-Inverted
Data 2
Data 3 Non-Inverted
Data 3
Data 4 Non-Inverted
Data 4
(Same as Data Gate 1)
(Same as Data Gate 1)
(Same as Data Gate 1)
G1D2T
G1D2N
G1D3T
G1D3N
G1D4T
G1D4N
Inverted
Inverted
Inverted
Inverted
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[13]
CLCIN[14]
CLCIN[15]
CLCIN[3]
CLCIN[4]
CLCIN[11]
CLCIN[12]
CLCIN[18]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[19]
CLCIN[20]
CLCIN[17]
CLCIN[16]
DS3x (CLCxSEL<10:8>)
CLCIN[26]
CLCIN[29]
CLCIN[30]
CLCIN[31]
CLCIN[27]
CLCIN[28]
CLCIN[25]
CLCIN[24]
DS4x (CLCxSEL<14:12>)
000
111
000
111
000
111
000
111
(CLCxCONH<0>)