Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 182  2013 Microchip Technology Inc.
16.2 RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
16.2.1 REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through corre-
sponding register pointers. The RTCC Value register
window (RTCVALH and RTCVALL) uses the RTCPTRx
bits (RCFGCAL<9:8>) to select the desired Timer
register pair (see Table 16-1).
By writing the RTCVALH byte, the RTCC Pointer value,
the RTCPTR<1:0> bits decrement by one until they reach
‘00’. Once they reach ‘00’, the MINUTES and SECONDS
value will be accessible through RTCVALH and
RTCVALL until the pointer value is manually changed.
TABLE 16-1: RTCVAL REGISTER MAPPING
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTRx bits
(ALCFGRPT<9:8>) to select the desired Alarm
register pair (see Table 16-2).
By writing the ALRMVALH byte, the ALRMPTR<1:0>
bits (Alarm Pointer value) decrement by one until they
reach ‘00’. Once they reach ‘00’, the ALRMMIN and
ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL, until the pointer value is
manually changed.
TABLE 16-2: ALRMVAL REGISTER
MAPPING
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes, the ALRMPTR<1:0> value will be
decremented. The same applies to the RTCVALH or
RTCVALL bytes with the RTCPTR<1:0> being
decremented.
16.2.2 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (see Example 16-1 and Example 16-2).
16.2.3 SELECTING RTCC CLOCK SOURCE
There are four reference source clock options that can
be selected for the RTCC using the RTCCLK<1:0>
bits (RTCPWC<11:10>): 00 = Secondary Oscillator,
01 = LPRC, 10 = 50 Hz External Clock and 11 = 60 Hz
External Clock.
EXAMPLE 16-1: SETTING THE RTCWREN BIT IN ASSEMBLY
EXAMPLE 16-2: SETTING THE RTCWREN BIT IN ‘C’
RTCPTR<1:0>
RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00 MINUTES SECONDS
01 WEEKDAY HOURS
10 MONTH DAY
11 —YEAR
ALRMPTR
<1:0>
Alarm Value Register Window
ALRMVALH<15:8> ALRMVALL<7:0>
00 ALRMMIN ALRMSEC
01 ALRMWD ALRMHR
10 ALRMMNTH ALRMDAY
11 PWCSTAB PWCSAMP
Note: This only applies to read operations and
not write operations.
Note: To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN.
Therefore, it is recommended that code
follow the procedure in Example 16-2.
push w7 ; Store W7 and W8 values on the stack.
push w8
disi #5 ; Disable interrupts until sequence is complete.
mov #0x55, w7 ; Write 0x55 unlock value to NVMKEY.
mov w7, NVMKEY
mov #0xAA, w8 ; Write 0xAA unlock value to NVMKEY.
mov w8, NVMKEY
bset RCFGCAL, #13 ; Set the RTCWREN bit.
pop w8 ; Restore the original W register values from the stack.
pop w7
//This builtin function executes implements the unlock sequence and sets
//the RTCWREN bit.
__builtin_write_RTCWEN();