Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 156  2013 Microchip Technology Inc.
REGISTER 13-5: CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DT5 DT4 DT3 DT2 DT1 DT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 DT<5:0>: CCPx Dead-Time Select bits
111111 = Insert 63 dead-time delay periods between complementary output signals
111110 = Insert 62 dead-time delay periods between complementary output signals
. . .
000010 = Insert 2 dead-time delay periods between complementary output signals
000001 = Insert 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
Note 1: This register is implemented in MCCPx modules only.