Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 148  2013 Microchip Technology Inc.
13.4 Input Capture Mode
Input Capture mode is used to capture a timer value
from an independent timer base upon an event on an
input pin or other internal Trigger source. The input
capture features are useful in applications requiring
frequency (time period) and pulse measurement.
Figure 13-6 depicts a simplified block diagram of Input
Capture mode.
Input Capture mode uses a dedicated 16/32-bit, synchro-
nous, up counting timer for the capture function. The timer
value is written to the FIFO when a capture event occurs.
The internal value may be read (with a synchronization
delay) using the CCPxTMRH/L register.
To use Input Capture mode, the CCSEL bit
(CCPxCON1L<4>) must be set. The T32 and the
MOD<3:0> bits are used to select the proper Capture
mode, as shown in Tab le 13- 4 .
FIGURE 13-6: INPUT CAPTURE x BLOCK DIAGRAM
TABLE 13-4: INPUT CAPTURE MODES
MOD<3:0>
(CCPxCON1L<3:0>)
T32
(CCPxCON1L<5>)
Operating Mode
0000 0 Edge Detect (16-bit capture)
0000 1 Edge Detect (32-bit capture)
0001 0 Every Rising (16-bit capture)
0001 1 Every Rising (32-bit capture)
0010 0 Every Falling (16-bit capture)
0010 1 Every Falling (32-bit capture)
0011 0 Every Rise/Fall (16-bit capture)
0011 1 Every Rise/Fall (32-bit capture)
0100 0 Every 4th Rising (16-bit capture)
0100 1 Every 4th Rising (32-bit capture)
0101 0 Every 16th Rising (16-bit capture)
0101 1 Every 16th Rising (32-bit capture)
CCPxBUFx
4-Level FIFO Buffer
MOD<3:0>
Set CCPxIF
OPS<3:0>
Interrupt
Logic
System Bus
Event and
Trigger and
Sync Logic
Clock
Select
IC Clock
Sources
Trigger and
Sync Sources
IC<2:0>
16
16
16
CCPxTMRH/L
Increment
Reset
T32
Edge Detect Logic
and
Clock Synchronizer