Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 144  2013 Microchip Technology Inc.
13.1 Time Base Generator
The Timer Clock Generator (TCG) generates a clock
for the module’s internal time base, using one of the
clock signals already available on the microcontroller.
This is used as the time reference for the module in its
three major modes. The internal time base is shown in
Figure 13-2.
There are eight inputs available to the clock generator,
which are selected using the CLKSEL<2:0> bits
(CCPxCON1L<10:8>). Available sources include the
FRC and LPRC, the Secondary Oscillator, and the TCLKI
External Clock inputs. The system clock is the default
source (CLKSEL<2:0> = 000). On PIC24FV16KM204
family devices, clock sources to the MCCPx module
must be synchronized with the system clock; as a result,
when clock sources are selected, clock input timing
restrictions or module operating restrictions may exist.
Ta bl e 13 -1 describes which time base sources are valid
for the various operating modes.
TABLE 13-1: VALID TIMER OPTIONS FOR
MCCPx/SCCPx MODES
FIGURE 13-2: TIMER CLOCK GENERATOR
CLKSEL
<2:0>
(1)
Timer
Input
Capture
Output
Compare
Sync
(2)
Async
(3)
111 X———
110 X———
101 X———
011 X———
010 X———
001 X———
000
(4)
—XX X
Note 1: See Register 13-1 for the description of
the time base sources.
2: Synchronous Operation: TMRSYNC
(CCPxCON1L<11>) = 1 and TRIGEN
(CCPxCON1H<7>) = 0.
3: Asynchronous Operation:
(TMRSYNC = 0) or Triggered mode
(TRIGEN = 1).
4: When CLKSEL<2:0> = 000, the
TMRSYNC bit must be cleared.
CLKSEL<2:0>
TMRPS<1:0>
Prescaler
Clock
Synchronizer
TMRSYNC
Gate
(1)
SSDG
Clock
Sources
To R e s t
of Module
Note 1: Gating available in Timer modes only.