Datasheet

PIC24FV16KM204 FAMILY
DS30003030B-page 100  2013 Microchip Technology Inc.
REGISTER 8-14: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — CCT5IE —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9 CCT5IE: Capture/Compare 5 Timer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-0 Unimplemented: Read as ‘0’
REGISTER 8-15: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—RTCIE— — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — — BCL2IE SSP2IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-3 Unimplemented: Read as ‘0’
bit 2 BCL2IE: MSSP2 I
2
C™ Bus Collision Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 SSP2IE: MSSP2 SPI/I
2
C Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 Unimplemented: Read as ‘0’