PIC24FV16KM204 FAMILY General Purpose, 16-Bit Flash Microcontrollers with XLP Technology Data Sheet Analog Peripheral Features High-Performance RISC CPU • Up to Two 8-Bit Digital-to-Analog Converters (DACs): - Soft Reset disable function allows DAC to retain its output value through non-VDD Resets - Support for Idle mode - Support for left and right justified input data • Two Operational Amplifiers (Op Amps): - Differential inputs - Selectable power/speed levels: - Low power/low speed - High power/high sp
PIC24FV16KM204 FAMILY Peripherals 8-Bit DAC Op Amp Comparators CTMU RTCC CLC 1 3/2 2 2 22 2 2 3 Yes Yes 2 3 2.0-5.5 1 3/2 2 2 19 2 2 3 Yes Yes 2 3 PIC24FV08KM204 44 8K 2K 512 2.0-5.5 1 3/2 2 2 22 2 2 3 Yes Yes 2 3 PIC24FV08KM202 28 8K 2K 512 2.0-5.5 1 3/2 2 2 19 2 2 3 Yes Yes 2 3 PIC24FV16KM104 44 16K 1K 512 2.0-5.5 1 1/1 1 1 22 — — 1 Yes — 1 3 PIC24FV16KM102 28 16K 1K 512 2.0-5.
PIC24FV16KM204 FAMILY Peripheral Features Special Microcontroller Features • High-Current Sink/Source, 18 mA/18 mA All Ports • Independent Ultra Low-Power, 32 kHz Timer Oscillator • Up to Two Master Synchronous Serial Ports (MSSPs) with SPI and I2C™ modes: In SPI mode: - User-configurable SCKx and SDOx pin outputs - Daisy-chaining of SPI slave devices In I2 C mode: - Serial clock synchronization (clock stretching) - Bus collision detection and will arbitrate accordingly - Support for 16-bit read/write int
PIC24FV16KM204 FAMILY 20-Pin PDIP/SSOP/SOIC RA5 RA0 RA1 RB0 RB1 RB2 RA2 RA3 RB4 RA4 1 2 3 4 5 6 7 8 9 10 PIC24F08KM101 Pin Diagrams 20 19 18 17 16 15 14 13 12 11 VDD VSS RB15 RB14 RB13 RB12 RA6 OR VDDCORE RB9 RB8 RB7 Pin Features Pin PIC24F08KM101 1 MCLR/VPP/RA5 2 PGEC2/CVREF+/VREF+/AN0/CN2/RA0 3 PGED2/CVREF-/VREF-/AN1/CN3/RA1 4 PGED1/AN2/CTCMP/ULPWU/C1IND/OC2A/CN4/RB0 5 PGEC1/AN3/C1INC/CTED12/CN5/RB1 6 AN4/U1RX/TCKIB/CTED13/CN6/RB2 7 OSCI/CLKI/AN13/C1INB/CN30/RA2 8 OSCO/CLKO/AN14/C1INA
PIC24FV16KM204 FAMILY CVREF- 20 19 18 17 16 RA5 CVREF+ RB0 1 RA0 20-Pin QFN RA1 Pin Diagrams (Continued) 15 RB1 2 RB15 14 RB14 RB2 3 PIC24F08KM101 13 RB13 RA2 4 8 RB7 9 10 RB9 7 RB8 6 RA4 12 RB12 RB4 RA3 5 11 RA6 or VDDCORE Pin Features Pin PIC24F08KM101 1 PGED1/AN2/CTCMP/ULPWU/C1IND/OC2A/CN4/RB0 2 PGEC1/AN3/C1INC/CTED12/CN5/RB1 3 AN4/U1RX/TCKIB/CTED13/CN6/RB2 4 OSCI/CLKI/AN13/C1INB/CN30/RA2 5 OSCO/CLKO/AN14/C1INA/CN29/RA3 6 PGED3/SOSCI/AN15/CLCINA/CN1/RB4 7 PGEC3/SOS
PIC24FV16KM204 FAMILY 28-Pin SPDIP/SSOP/SOIC MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24F16KMX02 Pin Diagrams (Continued) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS RB15 RB14 RB13 RB12 RB11 RB10 RA6 or VDDCORE RA7 RB9 RB8 RB7 RB6 Pin Features Pin PIC24FXXKMX02 1 MCLR/VPP/RA5 2 CVREF+/VREF+/DAC1REF+/AN0/C3INC/CN2/RA0 PIC24FVXXKMX02 3 CVREF-/VREF-/AN1/CN3/RA1 4 PGED1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0 5 PGEC1/OA1INA/
PIC24FV16KM204 FAMILY RA1 RA0 MCLR/RA5 VDD VSS RB15 RB14 Pin Diagrams (Continued) 28-Pin QFN(1) 28 27 26 25 24 23 22 1 21 2 20 3 PIC24F16KMX02 19 4 18 5 17 6 16 7 15 8 9 10 11 12 13 14 RB13 RB12 RB11 RB10 RA6 OR VDDCORE RA7 RB9 RB4 RA4 VDD RB5 RB6 RB7 RB8 RB0 RB1 RB2 RB3 VSS RA2 RA3 Pin Features Pin Features PIC24FXXKMX02 PIC24FVXXKMX02 Pin 1 PGED1/AN2/CTCMP/ULPWU/C1IND/C2INB/C3IND/U2TX/CN4/RB0 2 PGEC1/OA1INA/OA2INA/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 3 OA1INB/OA2INB/AN4/C1INB/C2IND/SDA2/U1RX
PIC24FV16KM204 FAMILY Pin Diagrams (Continued) Pin Features 44-Pin TQFP/QFN(1) Pin PIC24FXXKMX04 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 AVSS AVDD MCLR/RA5 RA0 RA1 RB0 RB1 RB9 RC6 RC7 RC8 RC9 RA7 RA6 RB10 RB11 RB12 RB13 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 PIC24FXXKMX04 Legend: Values in red indicate pin function differences between PIC24F(V)X
PIC24FV16KM204 FAMILY Pin Diagrams (Continued) Pin Features 48-Pin UQFN(1) RB8 RB7 RB6 RB5 n/c VDD VSS RC5 RC4 RC3 RA9 RA4 AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9 2 U1RX/OC2C/CN18/RC6 48 47 46 45 44 43 42 41 40 39 38 37 PIC24FVXXKMX04 1 3 U1TX/OC2D/CN17/RC7 4 OC2/CN20/RC8 5 IC4/OC2F/CTED7/CN19/RC9 6 IC1/OC5/CLC2O/CTED3/CN9/RA7 PIC24FXXKMX04 PIC24FVXXKMX04 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 PIC24FXXKMX04 36 35 34 33 32 31 30 29 28 27 26 25 RB4
PIC24FV16KM204 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 29 3.0 CPU ....................................................................................................
PIC24FV16KM204 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 12 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FV08KM101 • PIC24F08KM101 • PIC24FV08KM102 • PIC24F08KM102 • PIC24FV16KM102 • PIC24F16KM102 • PIC24FV16KM104 • PIC24F16KM104 • PIC24FV08KM202 • PIC24F08KM202 • PIC24FV08KM204 • PIC24F08KM204 • PIC24FV16KM202 • PIC24F16KM202 • PIC24FV16KM204 • PIC24F16KM204 The PIC24FV16KM204 family introduces many new analog features to the extreme low-power Microchip devices.
PIC24FV16KM204 FAMILY 1.1.4 EASY MIGRATION The PIC24FV16KM204 family devices have two variants. The KM20X variant provides the full feature set of the device, while the KM10X offers a reduced peripheral set, allowing for the balance of features and cost (refer to Table 1-1). Both variants allow for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also helps in migrating to the next larger device.
PIC24FV16KM204 FAMILY PIC24F08KM202 Operating Frequency PIC24F16KM202 Features PIC24F08KM204 DEVICE FEATURES FOR THE PIC24F16KM204 FAMILY PIC24F16KM204 TABLE 1-1: 16K 8K 5632 2816 DC-32 MHz Program Memory (bytes) 16K 8K Program Memory (instructions) 5632 2816 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) 40 (36/4) Voltage Range 1.8-3.
PIC24FV16KM204 FAMILY PIC24F08KM101 Operating Frequency PIC24F08KM102 Features PIC24F16KM102 DEVICE FEATURES FOR THE PIC24F16KM104 FAMILY PIC24F16KM104 TABLE 1-2: 8K 8K 2816 2816 DC-32 MHz Program Memory (bytes) 16K 16K Program Memory (instructions) 5632 5632 Data Memory (bytes) 1024 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) 25 (21/4) Voltage Range 1.8-3.
PIC24FV16KM204 FAMILY Operating Frequency PIC24FV08KM202 PIC24FV16KM202 Features PIC24FV08KM204 DEVICE FEATURES FOR THE PIC24FV16KM204 FAMILY PIC24FV16KM204 TABLE 1-3: DC-32 MHz Program Memory (bytes) 16K 8K 16K 8K Program Memory (instructions) 5632 2816 5632 2816 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) 40 (36/4) Voltage Range 2.0-5.
PIC24FV16KM204 FAMILY Operating Frequency PIC24FV08KM101 PIC24FV08KM102 Features PIC24FV16KM102 DEVICE FEATURES FOR THE PIC24FV16KM104 FAMILY PIC24FV16KM104 TABLE 1-4: DC-32 MHz Program Memory (bytes) 16K 16K 8K 8K Program Memory (instructions) 5632 5632 2816 2816 Data Memory (bytes) 1024 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) 25 (21/4) Voltage Range 2.0-5.
PIC24FV16KM204 FAMILY FIGURE 1-1: PIC24FXXXXX FAMILY GENERAL BLOCK DIAGRAMS Data Bus Interrupt Controller 16 16 8 16 Data Latch PSV and Table Data Access Control Block Data RAM PCL PCH Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTA(1) RA<0:7> 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) Data EEPROM RB<0:15> Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTC(1) RC<9:0> Inst Register Instruction Decode and Con
Function PIC24FV16KM204 FAMILY PINOUT DESCRIPTION F FV Pin Number Pin Number I/O Buffer 21 I ANA 22 I ANA A/D Analog Inputs 21 23 I ANA A/D Analog Inputs 2 22 24 I ANA A/D Analog Inputs 3 23 25 I ANA A/D Analog Inputs 7 4 24 26 I ANA A/D Analog Inputs — — — 25 27 I ANA A/D Analog Inputs 28 — — — 26 28 I ANA A/D Analog Inputs 27 29 — — — 27 29 I ANA A/D Analog Inputs 23 15 16 18 26 23 15 16 I ANA A/D Analog Inputs 25 22 14 15 17
2013 Microchip Technology Inc.
Function PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) F FV Pin Number Pin Number I/O Buffer 12 I ST Interrupt-on-Change Inputs 11 I ST Interrupt-on-Change Inputs 9 10 I ST Interrupt-on-Change Inputs 18 8 9 I ST Interrupt-on-Change Inputs — — 3 3 I ST Interrupt-on-Change Inputs — — — 2 2 I ST Interrupt-on-Change Inputs 5 — — — 5 5 I ST Interrupt-on-Change Inputs 4 4 — — — 4 4 I ST Interrupt-on-Change Inputs 15 1 1 13 18 15 1 1 I ST
2013 Microchip Technology Inc.
Function PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) 20-Pin PDIP/ SSOP/ SOIC F FV Pin Number Pin Number 28-Pin PDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN I/O 20-Pin PDIP/ SSOP/ SOIC 28-Pin PDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN Buffer Description Master Clear (Device Reset) Input (active-low) MCLR 1 1 26 18 19 1 1 26 18 19 I ST OA1INA — 5 2 22 24 — 5 2 22 24 I ANA OA1INB — 6 3 23 25 — 6 3 23 25 I ANA Op Amp 1
2013 Microchip Technology Inc.
Function PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) F FV Pin Number Pin Number I/O Buffer Description 20-Pin PDIP/ SSOP/ SOIC 28-Pin PDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin PDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN RB9 13 18 15 1 1 13 18 15 1 1 I/O ST PORTB Pins RB10 — 21 18 8 9 — 21 18 8 9 I/O ST PORTB Pins 2013 Microchip Technology Inc.
2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 28 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pins (see Section 2.
PIC24FV16KM204 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 µF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FV16KM204 FAMILY Voltage Regulator Pin (VCAP) Note: This section applies only to PIC24FV16KM devices with an on-chip voltage regulator. Refer to Section 27.0 “Electrical Characteristics” for information on VDD and VDDCORE. FIGURE 2-3: Some of the PIC24FV16KM devices have an internal voltage regulator. These devices have the voltage regulator output brought out on the VCAP pin.
PIC24FV16KM204 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24FV16KM204 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator (refer to for Section 9.0 “Oscillator Configuration”details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 34 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “PIC24F Family Reference Manual”, “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24FV16KM204 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data EEPROM EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Literal Data 16 Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 1
PIC24FV16KM204 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Regi
PIC24FV16KM204 FAMILY 3.
PIC24FV16KM204 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority
PIC24FV16KM204 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24FV16KM204 FAMILY 4.0 MEMORY ORGANIZATION As with Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and busing. This architecture also allows the direct access of program memory from the Data Space (DS) during code execution. 4.1 Program Address Space The user access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh).
PIC24FV16KM204 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24FV16KM204 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24FV16KM204 FAMILY 4.2 4.2.1 Data Address Space DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit-wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the Data Space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The PIC24F core has a separate, 16-bit-wide data memory space, addressable as a single linear range.
PIC24FV16KM204 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® devices and improve Data Space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory.
2013 Microchip Technology Inc. TABLE 4-3: File Name Addr.
ICN REGISTER MAP File Name Addr.
2013 Microchip Technology Inc. TABLE 4-5: File Name Addr.
File Name TIMER1 REGISTER MAP Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TMR1 100h Timer1 Register PR1 102h Timer1 Period Register T1CON 104h Legend: TON — TSIDL — — — TECS1 TECS0 — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 All Resets x = unknown, u = unchanged, — = unimplemented, q = value depends on condition, r = reserved. TABLE 4-7: File Name CLC1-2 REGISTER MAP Addr.
2013 Microchip Technology Inc. TABLE 4-8: File Name Addr.
File Name Addr.
2013 Microchip Technology Inc. TABLE 4-10: MCCP3 REGISTER MAP File Name Addr.
SCCP4 REGISTER MAP File Name Addr.
2013 Microchip Technology Inc. TABLE 4-12: File Name SCCP5 REGISTER MAP Addr.
File Name MSSP1 (I2C™/SPI) REGISTER MAP Addr.
2013 Microchip Technology Inc. TABLE 4-15: UART1 REGISTER MAP File Name Addr.
OP AMP 1 REGISTER MAP File Name Addr. Bit 15 Bit 14 AMP1CON(1) 24Ah AMPEN — Legend: Note 1: AMPSIDL AMPSLP Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — — — SPDSEL — NINSEL2 Bit 3 Bit 1 Bit 0 All Resets PINSEL1 PINSEL0 0000 Bit 1 Bit 0 All Resets PINSEL1 PINSEL0 0000 Bit 2 NINSEL1 NINSEL0 PINSEL2 OP AMP 2 REGISTER MAP File Name Addr.
2013 Microchip Technology Inc. TABLE 4-21: PORTA REGISTER MAP File Name Addr.
PAD CONFIGURATION REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 PADCFG1 2FCh — — — — SDO2DIS(1) Legend: Note 1: Bit 10 Bit 9 SCK2DIS(1) SDO1DIS Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets SCK1DIS — — — — — — — — 0000 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition, r = reserved. These bits are not available on the PIC24F(V)08KM101 device, read as ‘0’.
2013 Microchip Technology Inc.
CTMU REGISTER MAP File Name Addr.
2013 Microchip Technology Inc. TABLE 4-29: File Name COMPARATOR REGISTER MAP Addr.
File Name CLOCK CONTROL REGISTER MAP Addr.
PIC24FV16KM204 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as depicted in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FV16KM204 FAMILY TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:
PIC24FV16KM204 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through Data Space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.
PIC24FV16KM204 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of Data Space may optionally be mapped into a 16K word page of the program space. This provides transparent access of stored constant data from the Data Space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the Data Space occurs if the MSb of the Data Space, EA, is ‘1’ and PSV is enabled by setting the PSV bit in the CPU Control (CORCON<2>) register.
PIC24FV16KM204 FAMILY 5.0 Note: Run-Time Self-Programming (RTSP) is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes) at a time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes) at a time. FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV16KM204 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time, and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks, and single row write block (96 bytes) are edge-aligned, from the beginning of program memory.
PIC24FV16KM204 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, r
PIC24FV16KM204 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOPx bits (NVMCON<5:0>) to ‘011000’ to configure for row erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.
PIC24FV16KM204 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x1500, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,
PIC24FV16KM204 FAMILY EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 ; Block all interrupts for next 5 instructions MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2 EXAMPLE 5-6: ; ; ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence 2 NOPs required after setting WR Wait for the sequence to be completed INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 a
PIC24FV16KM204 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on data EEPROM, refer to the “PIC24F Family Reference Manual”, “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM.
PIC24FV16KM204 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable Only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
PIC24FV16KM204 FAMILY 6.3 NVM Address Register 6.4 As with Flash program memory, the NVM Address registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
PIC24FV16KM204 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP<1:0> (NVMCON<1:0>), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1. 2. 3. 4. 5. 6. Configure NVMCON to erase the required number of words: one, four or eight. Load TBLPAG and WREG with the EEPROM address to be erased.
PIC24FV16KM204 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing a bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear the NVMIF status bit and enable the NVM interrupt (optional).
PIC24FV16KM204 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the Table Read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location, followed by a TBLRDL instruction.
PIC24FV16KM204 FAMILY 7.0 Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets. RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV16KM204 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 7-1: R/W-0, HS R/W-0, HS R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR SBOREN RETEN(3) — — CM PMSLP bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleare
PIC24FV16KM204 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set a
PIC24FV16KM204 FAMILY 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the Oscillator Configuration bits. For more information, see Section 9.0 “Oscillator Configuration”. TABLE 7-2: OSCILLATOR SELECTION vs.
PIC24FV16KM204 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FV16KM204 FAMILY 7.4.2 SOFTWARE ENABLED BOR When BOREN<1:0> = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<13>). Setting SBOREN enables the BOR to function as previously described. Clearing the SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise, it is read as ‘0’.
PIC24FV16KM204 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “PIC24F Family Reference Manual”, “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24FV16KM204 FAMILY Decreasing Natural Order Priority FIGURE 8-1: DS30003030B-page 86 PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector
PIC24FV16KM204 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source Vector Number IVT Address AIVT Address Interrupt Bit Locations Flag En
PIC24FV16KM204 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FV16KM204 family of devices implements a total of 33 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS6 IEC0 through IEC6 IPC0 through IPC7, IPC10, IPC12, IPC15, IPC16, IPC18 through IPC20 and IPC24 • INTTREG Global Interrupt Enable (GIE) control functions are controlled from INTCON1 and INTCON2.
PIC24FV16KM204 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9
PIC24FV16KM204 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Prior
PIC24FV16KM204 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interru
PIC24FV16KM204 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 =
PIC24FV16KM204 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF U-0 — U-0 — R/W-0, HS CCT2IF bit 8 R/W-0, HS CCT1IF bit 7 R/W-0, HS CCP4IF R/W-0, HS CCP3IF U-0 — R/W-0, HS T1IF R/W-0, HS CCP2IF R/W-0, HS CCP1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 HS = Hardware Set
PIC24FV16KM204 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 U-0 U2TXIF U2RXIF INT2IF CCT4IF CCT3IF — — — bit 15 bit 8 U-0 R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — CCP5IF — INT1IF CNIF CMIF BCL1IF SSP1IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl
PIC24FV16KM204 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0 — — — — — — CCT5IF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 CCT5IF: Capture/Compare 5 Timer Interrupt Flag Status
PIC24FV16KM204 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS DAC2IF DAC1IF CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 — — — — — U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DAC2IF: Digital-to-Analog Converter
PIC24FV16KM204 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — ULPWUIF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Stat
PIC24FV16KM204 FAMILY REGISTER 8-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE U-0 — U-0 — R/W-0 CCT2IE bit 8 R/W-0 CCT1IE bit 7 R/W-0 CCP4IE R/W-0 CCP3IE U-0 — R/W-0 T1IE R/W-0 CCP2IE R/W-0 CCP1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, rea
PIC24FV16KM204 FAMILY REGISTER 8-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U2TXIE U2RXIE INT2IE CCT4IE CCT3IE — — — bit 15 bit 8 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CCP5IE — INT1IE CNIE CMIE BCL1IE SSP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Int
PIC24FV16KM204 FAMILY REGISTER 8-14: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — CCT5IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 CCT5IE: Capture/Compare 5 Timer Interrupt Enable bit 1 = Interrupt request is enab
PIC24FV16KM204 FAMILY REGISTER 8-16: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 DAC2IE DAC1IE CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DAC2IE: Digital-to-Analog Converter 2 Interrupt Enable bit 1 = Interrupt request is e
PIC24FV16KM204 FAMILY REGISTER 8-17: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit 1 = Interrupt request is ena
PIC24FV16KM204 FAMILY REGISTER 8-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — CCP2IP2 CCP2IP1 CCP2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CCP1IP2 CCP1IP1 CCP1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-
PIC24FV16KM204 FAMILY REGISTER 8-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CCT1IP2 CCT1IP1 CCT1IP0 — CCP4IP2 CCP4IP1 CCP4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CCP3IP2 CCP3IP1 CCP3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CCT1IP<2:0>: C
PIC24FV16KM204 FAMILY REGISTER 8-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1RXIP2 U1RXIP1 U1RXIP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — CCT2IP2 CCT2IP1 CCT2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt
PIC24FV16KM204 FAMILY REGISTER 8-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inte
PIC24FV16KM204 FAMILY REGISTER 8-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — BCL1IP2 BCL1IP1 BCL1IP0 — SSP1IP2 SSP1IP1 SSP1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CN
PIC24FV16KM204 FAMILY REGISTER 8-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — CCP5IP2 CCP5IP1 CCP5IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 CCP5IP<2:0>: Capture/Compare 5 Event
PIC24FV16KM204 FAMILY REGISTER 8-25: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CCT3IP2 CCT3IP1 CCT3IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CCT3IP<2:0>: Capture/Compare 3 Timer Interrupt Priority bits 1
PIC24FV16KM204 FAMILY REGISTER 8-26: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — CCT4IP2 CCT4IP1 CCT4IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ b
PIC24FV16KM204 FAMILY REGISTER 8-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CCT5IP2 CCT5IP1 CCT5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CCT5IP<2:0>: Capture/Compare 5 Timer Interrupt Priority bits
PIC24FV16KM204 FAMILY REGISTER 8-28: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — BCL2IP2 BCL2IP1 BCL2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SSP2IP2 SSP2IP1 SSP2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 BCL2IP<2:0>: MSSP2 I2C™ Bus Collis
PIC24FV16KM204 FAMILY REGISTER 8-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority b
PIC24FV16KM204 FAMILY REGISTER 8-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt
PIC24FV16KM204 FAMILY REGISTER 8-31: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24FV16KM204 FAMILY REGISTER 8-32: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DAC2IP2 DAC2IP1 DAC2IP0 — DAC1IP2 DAC1IP1 DAC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit
PIC24FV16KM204 FAMILY REGISTER 8-33: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ULPWUIP<2:0>: Ultra Low-Power Wake-up
PIC24FV16KM204 FAMILY REGISTER 8-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interr
PIC24FV16KM204 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 120 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 9.0 • On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources. • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for External Clock (EC) mode. When using an EC source, the current consumption is reduced by setting the declaration bits to the expected frequency range.
PIC24FV16KM204 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24FXXXXX family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24FV16KM204 FAMILY 9.3 The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): The FRC Oscillator Tune register (Register 9-3) allows the user to fine-tune the FRC Oscillator over a range of approximately ±5.25%.
PIC24FV16KM204 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is Enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FV16KM204 FAMILY REGISTER 9-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-1 DOZE2 DOZE1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, and
PIC24FV16KM204 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 TUN5 (1) R/W-0 (1) TUN4 R/W-0 (1) TUN3 R/W-0 TUN2 (1) R/W-0 TUN1 (1) R/W-0 TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillat
PIC24FV16KM204 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24FV16KM204 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8>, in two back-to-back instructions. Write the new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24FV16KM204 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referenc
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 130 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 10.0 POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Power-Saving Features with VBAT” (DS30622). Note: This FRM describes some features which are not implemented in this device. Sections related to the VBAT pin and Deep Sleep do not apply to the PIC24FV16KM204 family.
PIC24FV16KM204 FAMILY 10.2.2 IDLE MODE See Example 10-2 for initializing the ULPWU module. Idle mode includes these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.6 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FV16KM204 FAMILY REGISTER 10-1: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bi
PIC24FV16KM204 FAMILY 10.4 10.4.3 Voltage Regulator-Based Power-Saving Features The PIC24FV16KM204 family series devices have a voltage regulator that has the ability to alter functionality to provide power savings. The on-chip regulator is made up of two basic modules: the Voltage Regulator (VREG) and the Retention Regulator (RETREG). With the combination of VREG and RETREG, the following power modes are available: 10.4.
PIC24FV16KM204 FAMILY 10.5 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 136 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O ports, refer to the “PIC24F Family Reference Manual”, “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24FV16KM204 family devices do not support Peripheral Pin Select features.
PIC24FV16KM204 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION When reading the PORTx register, all pins configured as analog input channels will read as cleared (a low level). Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output.
PIC24FV16KM204 FAMILY REGISTER 11-2: ANSB: PORTB ANALOG SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 ANSB15 ANSB14 ANSB13 ANSB12 — — ANSB9 ANSB8 bit 15 bit 8 R/W-1 ANSB7 R/W-1 R/W-1 (1) ANSB5 ANSB6 (1) R/W-1 ANSB4 R/W-1 ANSB3 (1) R/W-1 R/W-1 R/W-1 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 ANSB<15:12>: Analog Select C
PIC24FV16KM204 FAMILY 11.2.2 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation, and a read operation of the same port. Typically, this instruction would be a NOP. 11.3 Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the PIC24FXXXXX family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins.
PIC24FV16KM204 FAMILY 12.0 Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. TIMER1 Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on timers, refer to the “PIC24F Family Reference Manual”, “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3.
PIC24FV16KM204 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — TECS1(1) TECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Uni
PIC24FV16KM204 FAMILY 13.0 Note: CAPTURE/COMPARE/PWM/ TIMER MODULES (MCCP AND SCCP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the MCCP/SCCP modules, refer to the “PIC24F Family Reference Manual”. PIC24FV16KM204 family devices include several Capture/Compare/PWM/Timer base modules, which provide the functionality of three different peripherals of earlier PIC24F devices.
PIC24FV16KM204 FAMILY 13.1 TABLE 13-1: Time Base Generator The Timer Clock Generator (TCG) generates a clock for the module’s internal time base, using one of the clock signals already available on the microcontroller. This is used as the time reference for the module in its three major modes. The internal time base is shown in Figure 13-2. There are eight inputs available to the clock generator, which are selected using the CLKSEL<2:0> bits (CCPxCON1L<10:8>).
PIC24FV16KM204 FAMILY 13.2 General Purpose Timer Timer mode is selected when CCSEL = 0 and MOD<3:0> = 0000. The timer can function as a 32-bit timer or a dual 16-bit timer, depending on the setting of the T32 bit (Table 13-2). TABLE 13-2: TIMER OPERATION MODE T32 (CCPxCON1L<5>) Operating Mode 0 Dual Timer Mode (16-bit) 1 Timer Mode (32-bit) Dual 16-Bit Timer mode provides a simple timer function with two independent 16-bit timer/counters. The primary timer uses CCPxTMRL and CCPxPRL.
PIC24FV16KM204 FAMILY FIGURE 13-4: SYNC<4:0> Clock Sources 32-BIT TIMER MODE Sync/ Trigger Control Time Base Generator CCPxTMRH CCPxTMRL Comparator CCPxPRH DS30003030B-page 146 Set CCTxIF CCPxPRL 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 13.3 pulses. Like most PIC® MCU peripherals, the Output Compare x module can also generate interrupts on a compare match event. Output Compare Mode Output Compare mode compares the Timer register value with the value of one or two Compare registers, depending on its mode of operation.
PIC24FV16KM204 FAMILY 13.4 Input Capture Mode Input Capture mode is used to capture a timer value from an independent timer base upon an event on an input pin or other internal Trigger source. The input capture features are useful in applications requiring frequency (time period) and pulse measurement. Figure 13-6 depicts a simplified block diagram of Input Capture mode. TABLE 13-4: Input Capture mode uses a dedicated 16/32-bit, synchronous, up counting timer for the capture function.
PIC24FV16KM204 FAMILY 13.5 Auxiliary Output The MCCPx and SCCPx modules have an auxiliary (secondary) output that provides other peripherals access to internal module signals. The auxiliary output is intended to connect to other MCCP or SCCP modules, or other digital peripherals, to provide these types of functions: The type of output signal is selected using the AUXOUT<1:0> control bits (CCPxCON2H<4:3>). The type of output signal is also dependent on the module operating mode.
PIC24FV16KM204 FAMILY REGISTER 13-1: R/W-0 CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS U-0 CCPON — R/W-0 CCPSIDL r-0 r R/W-0 TMRSYNC R/W-0 CLKSEL2 R/W-0 (1) R/W-0 (1) CLKSEL1 CLKSEL0(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRPS1 TMRPS0 T32 CCSEL MOD3 MOD2 MOD1 MOD0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
PIC24FV16KM204 FAMILY REGISTER 13-1: bit 3-0 Note 1: CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS (CONTINUED) MOD<3:0>: CCPx Mode Select bits For CCSEL = 1 (Input Capture modes): 1xxx = Reserved 011x = Reserved 0101 = Capture every 16th rising edge 0100 = Capture every 4th rising edge 0011 = Capture every rising and falling edge 0010 = Capture every falling edge 0001 = Capture every rising edge 0000 = Capture every rising and falling edge (Edge Detect mode) For CCSEL = 0 (Output Compare/Timer modes): 1111 = E
PIC24FV16KM204 FAMILY REGISTER 13-2: R/W-0 CCPxCON1H: CCPx CONTROL 1 HIGH REGISTERS R/W-0 OPSSRC(1) U-0 (2) RTRGEN — U-0 R/W-0 (3) — OPS3 R/W-0 OPS2 (3) R/W-0 OPS1 (3) R/W-0 OPS0(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGEN(4) ONESHOT ALTSYNC SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
PIC24FV16KM204 FAMILY TABLE 13-6: SYNCHRONIZATION SOURCES SYNC<4:0> 00000 None; Timer with Rollover on CCPxPR Match or FFFFh 00001 MCCP1 or SCCP1 Sync Output 00010 MCCP2 or SCCP2 Sync Output 00011 MCCP3 or SCCP3 Sync Output 00100 MCCP4 or SCCP4 Sync Output 00101 MCCP5 or SCCP5 Sync Output 00110 to 01010 01011 01100 to 10000 Unused Timer1 Sync Output(1) Unused 10001 CLC1 Output(1) 10010 CLC2 Output(1) 10011 to 11010 Note 1: Synchronization Source Unused 11011 A/D(1) 11110 Unused 1
PIC24FV16KM204 FAMILY REGISTER 13-3: CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 PWMRSEN ASDGM — SSDG — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ASDG7 ASDG6 ASDG5 ASDG4 ASDG3 ASDG2 ASDG1 ASDG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMRSEN: CCPx PWM Restart Enable bit 1 = A
PIC24FV16KM204 FAMILY REGISTER 13-4: R/W-0 CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS U-0 OENSYNC R/W-0 (1) — OCFEN R/W-0 (1) OCEEN R/W-0 OCDEN (1) R/W-0 (1) OCCEN R/W-0 (1) OCBEN R/W-0 OCAEN bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ICGSM1 ICGSM0 — AUXOUT1 AUXOUT0 ICS2 ICS1 ICS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OE
PIC24FV16KM204 FAMILY CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS (1) REGISTER 13-5: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DT5 DT4 DT3 DT2 DT1 DT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 DT<5:0>: CCPx Dead-Time Select bits 111111
PIC24FV16KM204 FAMILY REGISTER 13-6: R/W-0 CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS R/W-0 OETRIG R/W-0 OSCNT2 R/W-0 OSCNT1 U-0 OSCNT0 — R/W-0 OUTM2 R/W-0 (1) OUTM1 R/W-0 (1) OUTM0(1) bit 15 bit 8 U-0 U-0 — R/W-0 — POLACE R/W-0 R/W-0 (1) POLBDF PSSACE1 R/W-0 PSSACE0 R/W-0 PSSBDF1 R/W-0 (1) PSSBDF0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
PIC24FV16KM204 FAMILY REGISTER 13-7: CCPxSTATL: CCPx STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 W1-0 W1-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 CCPTRIG TRSET TRCLR ASEVT SCEVT ICDIS ICOV ICBNE bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W1 = Write ‘1’ only U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CCPTRIG: CCP
PIC24FV16KM204 FAMILY 14.0 Note: MASTER SYNCHRONOUS SERIAL PORT (MSSP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on MSSP, refer to the “PIC24F Family Reference Manual”. The Master Synchronous Serial Port (MSSP) module is an 8-bit serial interface, useful for communicating with other peripheral or microcontroller devices.
PIC24FV16KM204 FAMILY FIGURE 14-1: MSSPx BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read Write SSPxBUF SDIx SSPxSR bit 0 SDOx SSx Shift Clock SSx Control Enable Edge Select 2 Clock Select SMP:CKE 2 Edge Select SCKx SSPxADD<7:0> SSPM<3:0> 4 TMR2 Output 2 ( ) Prescaler TOSC 4, 16, 64 7 Baud Rate Generator Data to TX/RX in SSPxSR TRISx bit Note: Refer to the device data sheet for pin multiplexing.
PIC24FV16KM204 FAMILY FIGURE 14-3: MSSPx BLOCK DIAGRAM (I2C™ MODE) Internal Data Bus Read Write SSPxBUF Shift Clock SCLx SSPxSR SDAx MSb LSb Address Mask Match Detect Address Match SSPxADD Start and Stop bit Detect Note: Set/Reset S, P bits Only port I/O names are shown in this diagram. Refer to the text for a full list of multiplexed functions.
PIC24FV16KM204 FAMILY REGISTER 14-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 SMP R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 (1) D/A P S R/W UA BF CKE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is
PIC24FV16KM204 FAMILY REGISTER 14-2: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 SMP CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A (1) (1) R/W UA BF P S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Slew Rate Control bit In Master or Slav
PIC24FV16KM204 FAMILY REGISTER 14-2: bit 0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) (CONTINUED) BF: Buffer Full Status bit In Transmit mode: 1 = Transmit is in progress, SSPxBUF is full 0 = Transmit is complete, SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: 2: 3: This bit is cleared on Reset and when SSPEN is cleared.
PIC24FV16KM204 FAMILY REGISTER 14-3: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 WCOL R/W-0 R/W-0 (1) (2) SSPEN SSPOV R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7
PIC24FV16KM204 FAMILY SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) REGISTER 14-4: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WCOL:
PIC24FV16KM204 FAMILY REGISTER 14-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 GCEN
PIC24FV16KM204 FAMILY REGISTER 14-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 ACKTIM PCIE R/W-0 SCIE R/W-0 (1) BOEN R/W-0 R/W-0 R/W-0 R/W-0 SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge T
PIC24FV16KM204 FAMILY REGISTER 14-7: SSPxCON3: MSSPx CONTROL REGISTER 3 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM(1) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge
PIC24FV16KM204 FAMILY REGISTER 14-8: SSPxADD: MSSPx SLAVE ADDRESS/BAUD RATE GENERATOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 ADD<7:0>: Sl
PIC24FV16KM204 FAMILY REGISTER 14-10: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SDO2DIS(1) SCK2DIS(1) SDO1DIS SCK1DIS bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 SDO2DIS: MSSP2 SDO2 Pin Disable bit(1) 1 = The SP
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 172 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 15.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “PIC24F Family Reference Manual”, “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family.
PIC24FV16KM204 FAMILY 15.1 UARTx Baud Rate Generator (BRG) The UARTx module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 15-1 provides the formula for computation of the baud rate with BRGH = 0.
PIC24FV16KM204 FAMILY 15.2 1. 2. 3. 4. 5. 6. Set up the UARTx: a) Write the appropriate values for data, parity and Stop bits. b) Write the appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UARTx. Set the UTXEN bit (causes a transmit interrupt, two cycles after being set). Write the data byte to the lower byte of the UxTXREG word.
PIC24FV16KM204 FAMILY REGISTER 15-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FV16KM204 FAMILY REGISTER 15-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1
PIC24FV16KM204 FAMILY REGISTER 15-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 HC = Hardware Clearable bit Legend: HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writa
PIC24FV16KM204 FAMILY REGISTER 15-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the t
PIC24FV16KM204 FAMILY REGISTER 15-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x U-x U-x U-x U-x W-x — — — — — — — UTX8 bit 15 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) bit 7-0 UT
PIC24FV16KM204 FAMILY 16.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Real-Time Clock and Calendar, refer to the “PIC24F Family Reference Manual”, “Real-Time Clock and Calendar (RTCC)” (DS39696). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
PIC24FV16KM204 FAMILY 16.2 TABLE 16-2: RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 16.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTRx bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 16-1).
PIC24FV16KM204 FAMILY 16.2.
PIC24FV16KM204 FAMILY REGISTER 16-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 Note 1: 2: 3: CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . .
PIC24FV16KM204 FAMILY REGISTER 16-2: RTCPWC: RTCC CONFIGURATION REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1(2) RTCCLK0(2) RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCEN: Power Control Enable bit 1 = Power
PIC24FV16KM204 FAMILY REGISTER 16-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALR
PIC24FV16KM204 FAMILY 16.2.
PIC24FV16KM204 FAMILY WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 16-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<
PIC24FV16KM204 FAMILY 16.2.
PIC24FV16KM204 FAMILY REGISTER 16-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FV16KM204 FAMILY REGISTER 16-11: RTCCSWT: RTCC CONTROL/SAMPLE WINDOW TIMER REGISTER(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSTAB7 PWCSTAB6 PWCSTAB5 PWCSTAB4 PWCSTAB3 PWCSTAB2 PWCSTAB1 PWCSTAB0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSAMP7 PWCSAMP6 PWCSAMP5 PWCSAMP4 PWCSAMP3 PWCSAMP2 PWCSAMP1 PWCSAMP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24FV16KM204 FAMILY 16.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value, loaded into the lower half of RCFGCAL, is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute.
PIC24FV16KM204 FAMILY FIGURE 16-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: 16.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 194 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 17.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLC) module allows the user to specify combinations of signals as inputs to a logic function and to use the logic output to control other peripherals or I/O pins. This provides greater flexibility and potential in embedded designs since the CLC FIGURE 17-1: There are four input gates to the selected logic function.
PIC24FV16KM204 FAMILY FIGURE 17-2: CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS AND – OR OR – XOR Gate 1 Gate 1 Gate 2 Logic Output Gate 3 Gate 2 Logic Output Gate 3 Gate 4 Gate 4 MODE<2:0> = 000 MODE<2:0> = 001 4-Input AND S-R Latch Gate 1 Gate 1 Gate 2 Gate 2 Logic Output Gate 3 Gate 4 S Gate 3 Q R Gate 4 MODE<2:0> = 010 MODE<2:0> = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R Gate 4 D Gate 2 S Gate 4 Q Logic Output D Gate 2 Gate 1 Gate 1 Logic Output
PIC24FV16KM204 FAMILY FIGURE 17-3: CLCx INPUT SOURCE SELECTION DIAGRAM Data Selection CLCIN[0] CLCIN[1] CLCIN[2] CLCIN[3] CLCIN[4] CLCIN[5] CLCIN[6] CLCIN[7] 000 Data Gate 1 Data 1 Non-Inverted G1D1T Data 1 Inverted G1D1N 111 DS1x (CLCxSEL<2:0>) G1D2T G1D2N CLCIN[8] CLCIN[9] CLCIN[10] CLCIN[11] CLCIN[12] CLCIN[13] CLCIN[14] CLCIN[15] G1D3T Data 2 Non-Inverted Data 2 Inverted G1D4T G1D4N 000 Data Gate 2 Data 3 Non-Inverted Data 3 Inverted Gate 2 (Same as Data Gate 1) Data Gate 3 111 Gate 3
PIC24FV16KM204 FAMILY 17.1 The CLCx Source Select register (CLCxSEL) allows the user to select up to 4 data input sources using the 4 data input selection multiplexers. Each multiplexer has a list of 8 data sources available.
PIC24FV16KM204 FAMILY REGISTER 17-1: bit 2-0 CLCxCONL: CLCx CONTROL REGISTER (LOW) (CONTINUED) MODE<2:0>: CLCx Mode bits 111 = Cell is a 1-input transparent latch with S and R 110 = Cell is a JK flip-flop with R 101 = Cell is a 2-input D flip-flop with R 100 = Cell is a 1-input D flip-flop with S and R 011 = Cell is an SR latch 010 = Cell is a 4-input AND 001 = Cell is an OR-XOR 000 = Cell is a AND-OR REGISTER 17-2: CLCxCONH: CLCx CONTROL REGISTER (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — —
PIC24FV16KM204 FAMILY REGISTER 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — DS42 DS41 DS40 — DS32 DS31 DS30 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — DS22 DS21 DS20 — DS12 DS11 DS10 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DS4<2:0>: Data Selection MUX 4
PIC24FV16KM204 FAMILY REGISTER 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER (CONTINUED) bit 6-4 DS2<2:0>: Data Selection MUX 2 Signal Selection bits 111 = MCCP2 Compare Event Flag (CCP2IF) 110 = MCCP1 Compare Event Flag (CCP1IF) 101 = Digital logic low 100 = A/D end of conversion event For CLC1: 011 = UART1 TX 010 = Comparator 1 output 001 = CLC2 output 000 = CLCINB I/O pin For CLC2: 011 = UART2 TX 010 = Comparator 1 output 001 = CLC1 output 000 = CLCINB I/O pin bit 3 Unimplemented: Read as ‘0’ bit 2
PIC24FV16KM204 FAMILY REGISTER 17-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 G2D4T: Gate 2 Data So
PIC24FV16KM204 FAMILY REGISTER 17-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED) bit 3 G1D2T: Gate 1 Data Source 2 True Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 1 0 = The Data Source 2 inverted signal is disabled for Gate 1 bit 2 G1D2N: Gate 1 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 1 0 = The Data Source 2 inverted signal is disabled for Gate 1 bit 1 G1D1T: Gate 1 Data Source 1 True Enable bit 1 = The D
PIC24FV16KM204 FAMILY REGISTER 17-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 G4D4T: Gate 4 Data S
PIC24FV16KM204 FAMILY REGISTER 17-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED) bit 3 G3D2T: Gate 3 Data Source 2 True Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 3 0 = The Data Source 2 inverted signal is disabled for Gate 3 bit 2 G3D2N: Gate 3 Data Source 2 Negated Enable bit 1 = The Data Source 2 inverted signal is enabled for Gate 3 0 = The Data Source 2 inverted signal is disabled for Gate 3 bit 1 G3D1T: Gate 3 Data Source 1 True Enable bit 1 = The
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 206 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 18.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV16KM204 FAMILY REGISTER 18-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power En
PIC24FV16KM204 FAMILY 19.0 Note: 12-BIT A/D CONVERTER WITH THRESHOLD DETECT This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 12-Bit A/D Converter with Threshold Detect, refer to the “PIC24F Family Reference Manual”, “12-Bit A/D Converter with Threshold Detect” (DS39739).
PIC24FV16KM204 FAMILY FIGURE 19-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VREF- VR Select AVDD VR+ 16 VR- VBG Comparator VINH VINL AN0 VRS/H VR+ DAC AN1 10/12-Bit SAR AN2 Conversion Logic AN3 Data Formatting AN4 VINH AN6 AN7 MUX A AN5 ADC1BUF0: ADC1BUF17 AN8 AD1CON1 VINL AN9 AN21 CTMU Temp. Sensor CTMU MUX B AN20 AD1CON2 AD1CON3 AD1CON5 AD1CHS AD1CHITL AD1CHITH AD1CSSL AD1CSSH VINH VINL Sample Control VBG 0.
PIC24FV16KM204 FAMILY To perform an A/D conversion: 1. 2. Configure the A/D module: a) Configure the port pins as analog inputs and/or select band gap reference inputs (ANSx registers). b) Select the voltage reference source to match the expected range on the analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:4> and AD1CON3<12:8>).
PIC24FV16KM204 FAMILY 19.1 A/D Control Registers The 12-bit A/D Converter module uses up to 43 registers for its operation. All registers are mapped in the data memory space. 19.1.
PIC24FV16KM204 FAMILY REGISTER 19-1: AD1CON1: A/DA/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL — — MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x =
PIC24FV16KM204 FAMILY REGISTER 19-1: AD1CON1: A/DA/D CONTROL REGISTER 1 (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is manually set bit 1 SAMP: A/D Sample Enable bit 1 = A/D Sample-and-Hold amplifiers are sampling 0 = A/D Sample-and-Hold amplifiers are holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion cycle has completed 0 = A/D
PIC24FV16KM204 FAMILY REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 — BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: A/D Converter P
PIC24FV16KM204 FAMILY REGISTER 19-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Sou
PIC24FV16KM204 FAMILY REGISTER 19-4: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 R/W-0 ASEN(1) LPEN CTMREQ BGREQ r — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: A/D Auto-Scan Enable bit(1) 1 = Auto
PIC24FV16KM204 FAMILY REGISTER 19-5: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13
PIC24FV16KM204 FAMILY REGISTER 19-5: AD1CHS: A/D SAMPLE SELECT REGISTER (CONTINUED) bit 7-5 CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits The same definitions as for CHONB<2:0>. bit 4-0 CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits The same definitions as for CHONA<4:0>. Note 1: 2: 3: This is implemented on 44-pin devices only. This is implemented on 28-pin and 44-pin devices only.
PIC24FV16KM204 FAMILY REGISTER 19-7: AD1CHITL: A/D SCAN COMPARE HIT REGISTER (LOW WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH15 CHH14 CHH13 CHH12 CHH11 CHH10 CHH9 CHH8(2,3) bit 15 bit 8 R/W-0 CHH7 R/W-0 (2,3) CHH6 (2,3) R/W-0 CHH5 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH4 CHH3 CHH2 CHH1 CHH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note
PIC24FV16KM204 FAMILY REGISTER 19-8: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — CSS30 CSS29 CSS28 CSS27 CSS26 — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20(2) CSS19(2) CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bi
PIC24FV16KM204 FAMILY REGISTER 19-10: AD1CTMENH: CTMU ENABLE REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 CTMEN23 CTMEN22 CTMEN21 R/W-0 R/W-0 CTMEN20(2) CTMEN19(2) R/W-0 R/W-0 R/W-0 CTMEN18 CTMEN17 CTMEN16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’.
PIC24FV16KM204 FAMILY 19.2 A/D Sampling Requirements The analog input model of the 12-bit A/D Converter is shown in Figure 19-2. The total sampling time for the A/D is a function of the holding capacitor charge time. For the A/D Converter to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
PIC24FV16KM204 FAMILY 19.3 Transfer Function The transfer functions of the A/D Converter in 12-bit resolution are shown in Figure 19-3. The difference of the input voltages (VINH – VINL) is compared to the reference ((VR+) – (VR-)). • The first code transition occurs when the input voltage is ((VR+) – (VR-))/4096 or 1.0 LSb. • The ‘0000 0000 0001’ code is centered at VR- + (1.5 * ((VR+) – (VR-))/4096). FIGURE 19-3: • The ‘0010 0000 0000’ code is centered at VREFL + (2048.5 * ((VR+) – (VR-))/4096).
PIC24FV16KM204 FAMILY 19.4 conversions 11 bits wide. The signed decimal format yields 12-bit and 10-bit values, respectively. The Sign bit (bit 12 or bit 10) is sign-extended to fill the buffer. The FORM<1:0> bits (AD1CON1<9:8>) select the format. Figure 19-4 and Figure 19-5 show the data output formats that can be selected. Table 19-1 through Table 19-4 show the numerical equivalents for the various conversion result codes.
PIC24FV16KM204 FAMILY TABLE 19-2: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 12-BIT FRACTIONAL FORMATS 16-Bit Fractional Format/ Equivalent Decimal Value 12-Bit Output Code VIN/VREF 16-Bit Signed Fractional Format/ Equivalent Decimal Value +4095/4096 0 1111 1111 1111 1111 1111 1111 0000 0.999 0111 1111 1111 1000 0.999 +4094/4096 0 1111 1111 1110 1111 1111 1110 0000 0.998 0111 1111 1110 1000 0.998 +1/4096 0 0000 0000 0001 0000 0000 0001 0000 0.001 0000 0000 0000 1000 0.
PIC24FV16KM204 FAMILY TABLE 19-4: VIN/VREF NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT FRACTIONAL FORMATS 10-Bit Differential Output Code (11-bit result) 16-Bit Fractional Format/ Equivalent Decimal Value 16-Bit Signed Fractional Format/ Equivalent Decimal Value +1023/1024 011 1111 1111 1111 1111 1100 0000 0.999 0111 1111 1110 0000 0.999 +1022/1024 011 1111 1110 1111 1111 1000 0000 0.998 0111 1111 1000 0000 0.998 +1/1024 000 0000 0001 0000 0000 0100 0000 0.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 228 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 20.0 Note: The DAC generates an analog output voltage based on the digital input code, according to the formula: 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”. Device-specific information in this data sheet supersedes the information in the “PIC24F Family Reference Manual”.
PIC24FV16KM204 FAMILY REGISTER 20-1: DACxCON: DACx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 DACEN — DACSIDL DACSLP DACFM — SRDIS DACTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACOE DACTSEL4 DACTSEL3 DACTSEL2 DACTSEL1 DACTSEL0 DACREF1 DACREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DACEN: DAC
PIC24FV16KM204 FAMILY REGISTER 20-1: DACxCON: DACx CONTROL REGISTER (CONTINUED) bit 6-2 DACTSEL<4:0>: DACx Trigger Source Select bits 11101-11111 = Unused 11100 = CTMU 11011 = A/D 11010 = Comparator 3 11001 = Comparator 2 11000 = Comparator 1 10011 to 10111 = Unused 10010 = CLC2 output 10001 = CLC1 output 01100 to 10000 = Unused 01011 = Timer1 Sync output 01010 = External Interrupt 2 01001 = External Interrupt 1 01000 = External Interrupt 0 0011x = Unused 00101 = MCCP5 or SCCP5 Sync output 00100 = MCCP4
PIC24FV16KM204 FAMILY REGISTER 20-2: BUFCON0: INTERNAL VOLTAGE REFERENCE CONTROL REGISTER 0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — BUFREF1 BUFREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1-0 BUFREF<1:0>: Internal Voltage Reference Select bits 11 = Re
PIC24FV16KM204 FAMILY 21.0 Note: The two op amps are functionally identical; the block diagram for a single amplifier is shown in Figure 21-1. Each op amp has these features: DUAL OPERATIONAL AMPLIFIER MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Operational Amplifier (Op Amp)” (DS30505).
PIC24FV16KM204 FAMILY AMPxCON: OP AMP x CONTROL REGISTER(1) REGISTER 21-1: R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 AMPEN — AMPSIDL AMPSLP — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPDSEL — NINSEL2 NINSEL1 NINSEL0 PINSEL2 PINSEL1 PINSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AMPEN: Op Amp x Control Module Enabl
PIC24FV16KM204 FAMILY 22.0 COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, “Scalable Comparator Module” (DS39734). The comparator module provides three dual input comparators.
PIC24FV16KM204 FAMILY FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF<1:0> = xx, CCH<1:0> = xx COE VIN- – VIN+ Cx Off (Read as ‘0’) Comparator CxINC > CxINA Compare CON = 1, CREF<1:0> = 00, CCH<1:0> = 01 Comparator CxINB > CxINA Compare CON = 1, CREF<1:0> = 00, CCH<1:0> = 00 CXINB CXINA VIN- COE – VIN+ CXINC Cx CxOUT Pin Comparator CxIND > CxINA Compare CON = 1, CREF<1:0> = 00, CCH<1:0> = 10 CXIND CXINA VINVIN+ CVREF VIN- BGBUF1 Cx CxOUT Pin VIN+ DAC1O
PIC24FV16KM204 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0 CON COE CPOL CLPWR — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 (2) EVPOL1 EVPOL0 (2) U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — CREF1 CREF0 — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator x Enable bit 1 = Compa
PIC24FV16KM204 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator x Channel Select bits 11 = Inverting input of the comparator connects to BGBUF1(1) 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin Note 1: 2: BGBUF1 voltage is configured by BUFREF1<1:0> (BUFCON0<1:0>).
PIC24FV16KM204 FAMILY 23.0 Note: COMPARATOR VOLTAGE REFERENCE 23.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator Voltage Reference, refer to the “PIC24F Family Reference Manual”, “Comparator Voltage Reference Module” (DS39709). Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 23-1).
PIC24FV16KM204 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference
PIC24FV16KM204 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Time Measurement Unit, refer to the “PIC24F Family Reference Manual”, “Charge Time Measurement Unit (CTMU) with Threshold Detect” (DS39743).
PIC24FV16KM204 FAMILY FIGURE 24-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1STAT Current Source EDG2STAT Output Pulse A/D Converter ANx ANy CAPP 24.2 RPR Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s Internal Capacitor (CAD) and a precision resistor for current calibration.
PIC24FV16KM204 FAMILY 24.3 When the voltage on CDELAY equals CVREF, CTPLS goes low. With Comparator 2 configured as the second edge, this stops the CTMU from charging. In this state event, the CTMU automatically connects to ground. The IDISSEN bit doesn’t need to be set and cleared before the next CTPLS cycle. Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock.
PIC24FV16KM204 FAMILY REGISTER 24-1: CTMUCON1L: CTMU CONTROL 1 LOW REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1
PIC24FV16KM204 FAMILY REGISTER 24-1: bit 1-0 CTMUCON1L: CTMU CONTROL 1 LOW REGISTER (CONTINUED) IRNG<1:0>: Current Source Range Select bits 11 = 100 × Base Current 10 = 10 × Base Current 01 = Base Current Level (0.55 µA nominal) 00 = 1000 × Base Current 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY REGISTER 24-2: CTMUCON1H: CTMU CONTROL 1 HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FV16KM204 FAMILY REGISTER 24-2: CTMUCON1H: CTMU CONTROL 1 HIGH REGISTER (CONTINUED) bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge 0 = Edge 2 is programmed for a negative edge bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is the Comparator 3 output 1110 = Edge 2 source is the Comparator 2 output 1101 = Edge 2 source is the Comparator 1 output 1100 = Unimplemented; do not use 1011 = Edge 2 source is CLC1 1010 = Edge 2 source is the MCCP
PIC24FV16KM204 FAMILY REGISTER 24-3: CTMUCON2L: CTMU CONTROL 2 LOW REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — IRSTEN — DISCHS2 DISCHS1 DISCHS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 IRSTEN: CTMU Current Source Reset Enable b
PIC24FV16KM204 FAMILY 25.0 SPECIAL FEATURES Note: 25.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FV16KM204 FAMILY REGISTER 25-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GCP GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 GCP: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protecti
PIC24FV16KM204 FAMILY REGISTER 25-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits 1x = Clock switching is disabled,
PIC24FV16KM204 FAMILY REGISTER 25-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting
PIC24FV16KM204 FAMILY REGISTER 25-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE(2) BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN RETCFG(1) BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is di
PIC24FV16KM204 FAMILY REGISTER 25-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 DEBUG — — — — — FICD1 FICD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled bit 6-2 Unimplemented: Read as ‘0’
PIC24FV16KM204 FAMILY REGISTER 25-8: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bi
PIC24FV16KM204 FAMILY REGISTER 25-9: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Min
PIC24FV16KM204 FAMILY 25.2 On-Chip Voltage Regulator All of the PIC24FXXXXX family devices power their core digital logic at a nominal 3.0V. This may create an issue for designs that are required to operate at a higher typical voltage, as high as 5.0V. To simplify system design, all devices in the “FV” family incorporate an on-chip regulator that allows the device core to run at 3.0V, while the I/O is powered by VDD at a higher voltage.
PIC24FV16KM204 FAMILY The WDT, prescaler and postscaler are reset: 25.3.1 • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e.
PIC24FV16KM204 FAMILY 25.4 Program Verification and Code Protection For all devices in the PIC24FXXXXX family, code protection for the Boot Segment is controlled by the Configuration bit, BSS0, and the General Segment by the Configuration bit, GCP. These bits inhibit external reads and writes to the program memory space This has no direct effect in normal execution mode. Write protection is controlled by bit, BWRP, for the Boot Segment and bit, GWRP, for the General Segment in the Configuration Word.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 260 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 26.
PIC24FV16KM204 FAMILY 26.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC24FV16KM204 FAMILY 26.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FV16KM204 FAMILY 26.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC24FV16KM204 FAMILY 27.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FV16KM204 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FV16KM204 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FV16KM204 FAMILY 27.1 DC Characteristics Voltage (VDD) FIGURE 27-1: PIC24FV16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 5.5V 5.5V 3.20V 3.20V 2.00V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 2.0) + 8 MHz. Voltage (VDD) FIGURE 27-2: PIC24F16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.
PIC24FV16KM204 FAMILY Voltage (VDD) FIGURE 27-3: PIC24FV16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 5.5V 5.5V 3.20V 3.20V 2.00V 8 MHz 24 MHz Frequency Note: Voltage (VDD) FIGURE 27-4: For frequencies between 8 MHz and 24 MHz, FMAX = 13.33 MHz * (VDD – 2.0) + 8 MHz. PIC24F16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 24 MHz Frequency Note: For frequencies between 8 MHz and 24 MHz, FMAX = 13.33 MHz * (VDD – 1.8) + 8 MHz.
PIC24FV16KM204 FAMILY TABLE 27-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 27-2: THERMAL PACKAGING CHARACTERISTICS Characteristic
PIC24FV16KM204 FAMILY TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol No. DC18 VHLVD Characteristic HLVD Voltage on VDD Transition HLVDL<3:0> = 0000(2) Typ Max Units — — 1.90 V HLVDL<3:0> = 0001 1.88 — 2.13 V HLVDL<3:0> = 0010 2.09 — 2.35 V HLVDL<3:0> = 0011 2.25 — 2.
PIC24FV16KM204 FAMILY TABLE 27-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KMXXX) 2.0V to 5.5V (PIC24FV16KMXXX) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Typical Max Units Conditions 269 450 µA 2.0V 465 830 µA 5.0V 200 330 µA 1.8V 410 750 µA 3.3V 490 — µA 2.0V 880 — µA 5.0V 407 — µA 1.8V 800 — µA 3.
PIC24FV16KM204 FAMILY TABLE 27-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) DC CHARACTERISTICS Parameter No. Device Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KMXXX) 2.0V to 5.5V (PIC24FV16KMXXX) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Typical Max Units Conditions 120 200 µA 2.0V Idle Current (IIDLE) DC40 DC42 PIC24FV16KMXXX 160 430 µA 5.0V PIC24F16KMXXX 50 100 µA 1.8V 90 370 µA 3.3V PIC24FV16KMXXX 165 — µA 2.
PIC24FV16KM204 FAMILY TABLE 27-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typical(1) Device Max Units Conditions Power-Down Current (IPD) DC60 PIC24FV16KMXXX 6.0 — -40°C 8.0 +25°C 8.5 µA +85°C 15.0 +125°C — -40°C 8.0 6.0 PIC24F16KMXXX 0.025 9.0 DC61 PIC24FV16KMXXX 0.
PIC24FV16KM204 FAMILY TABLE 27-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typical(1) Max Units 0.50 — µA 2.0V 0.70 1.5 µA 5.0V PIC24F16KMXXX 0.50 — µA 1.8V 0.70 1.5 µA 3.3V PIC24FV16KMXXX 0.80 — µA 2.0V 1.50 2.0 µA 5.0V PIC24F16KMXXX 0.
PIC24FV16KM204 FAMILY TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(4) DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.
PIC24FV16KM204 FAMILY TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 OSC2/CLKO VOH DO20 Typ(1) Max — — 0.4 V IOL = 8.0 mA VDD = 4.5V — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V — — 0.4 V IOL = 2.0 mA VDD = 4.5V — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V 3.8 — — V IOH = -3.5 mA VDD = 4.5V 3 — — V IOH = -3.0 mA VDD = 3.6V 1.6 — — V IOH = -1.
PIC24FV16KM204 FAMILY TABLE 27-12: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym Min Typ(1) Max Units 100,000 — — E/W VMIN — 3.
PIC24FV16KM204 FAMILY TABLE 27-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) -40°C TA +125°C for Extended Param Symbol No. Characteristics Min Typ Max Units Comments VDD > 4.5V for 4*VBG reference VDD > 2.3V for 2*VBG reference VBG Band Gap Reference Voltage 0.973 1.024 1.075 V TBG Band Gap Reference Start-up Time — 1 — ms VRGOUT Regulator Output Voltage 3.1 3.3 3.6 V CEFC External Filter Capacitor Value 4.
PIC24FV16KM204 FAMILY TABLE 27-17: OPERATIONAL AMPLIFIER SPECIFICATIONS DC CHARACTERISTICS Param No. Note 1: Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ(1) Max Units 5 — MHz Comments GBWP Gain Bandwidth Product — — 0.5 — MHz SPDSEL = 0 SR Slew Rate — 1.2 — V/µs SPDSEL = 1 — 0.
PIC24FV16KM204 FAMILY 27.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FV16KM204 family AC characteristics and timing parameters. TABLE 27-18: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.
PIC24FV16KM204 FAMILY FIGURE 27-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 27-20: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (External Clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.
PIC24FV16KM204 FAMILY TABLE 27-21: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FV16KM204 FAMILY FIGURE 27-7: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value New Value DO31 DO32 Note: Refer to Figure 27-5 for load conditions. TABLE 27-24: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.
PIC24FV16KM204 FAMILY FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY FIGURE 27-9: BROWN-OUT RESET CHARACTERISTICS VDDCORE (Device not in Brown-out Reset) DC15 DC19 (Device in Brown-out Reset) SY25 Reset (Due to BOR) TVREG + TRST TABLE 27-25: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.
PIC24FV16KM204 FAMILY TABLE 27-26: COMPARATOR TIMING REQUIREMENTS Param No. Symbol Characteristic Min Typ Max Units 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 27-27: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No.
PIC24FV16KM204 FAMILY FIGURE 27-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 79 79 78 SCKx (CKP = 1) MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 27-5 for load conditions. TABLE 27-29: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC24FV16KM204 FAMILY FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 78 MSb SDOx LSb bit 6 - - - - - - 1 75, 76 SDIx bit 6 - - - - 1 MSb In LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-30: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC24FV16KM204 FAMILY FIGURE 27-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 27-5 for load conditions. TABLE 27-31: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC24FV16KM204 FAMILY FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 73 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 77 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-32: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC24FV16KM204 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 27-15: SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-33: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC24FV16KM204 FAMILY TABLE 27-34: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz MSSPx module 1.5 TCY — — 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz MSSPx module 1.
PIC24FV16KM204 FAMILY MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-17: SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-35: I2C™ BUS START/STOP BITS REQUIREMENTS (MASTER MODE) Param. Symbol No.
PIC24FV16KM204 FAMILY MSSPx I2C™ BUS DATA TIMING FIGURE 27-18: 103 102 100 101 SCLx 90 106 91 92 107 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 27-5 for load conditions. TABLE 27-36: I2C™ BUS DATA REQUIREMENTS (MASTER MODE) Param. Symbol No.
PIC24FV16KM204 FAMILY TABLE 27-37: A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204) 2.0V to 5.5V (PIC24FV16KM204) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ Max. Units Conditions Device Supply AD01 AD02 AVDD AVSS Module VDD Supply Module VSS Supply Greater of: VDD – 0.3 or 1.8 — Lesser of: VDD + 0.3 or 3.
PIC24FV16KM204 FAMILY FIGURE 27-19: A/D CONVERSION TIMING BSET AD1CON1, SAMP BCLR AD1CON1, SAMP (Note 2) AD55 Q3/Q4 AD58 A/D CLK AD59 AD50 (1) A/D DATA 11 10 9 ... ... 2 1 0 Old Data ADC1BUFx New Data AD1IF TCY SAMP Note 1: 2: Sampling Stopped If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC24FV16KM204 FAMILY TABLE 27-39: 8-BIT DIGITAL-TO-ANALOG CONVERTER SPECIFICATIONS AC CHARACTERISTICS Param No. Sym Characteristic Resolution Min. Typ 8 Max. Units — — bits DACREF<1:0> Input Voltage AVSS + 1.8 Range — AVDD V Differential Linearity Error (DNL) — — ±0.5 LSb Integral Linearity Error (INL) — — ±1.5 LSb Offset Error — — ±0.5 LSb Gain Error — — ±3.0 LSb — — — Monotonicity Output Voltage Range Note 1: Standard Operating Conditions: 1.8V to 3.
PIC24FV16KM204 FAMILY 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 20-Lead PDIP (300 mil) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24F08KM101 -I/P e3 1342M7W Example 24F08KM101 301-I/SS e3 1342M7W 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC24F08KM101 -I/SO e3 YYWWNNN 1342M7W 20-Lead QFN Example XXXXXXX XXXXXXX YYWWNNN Legend: XX...
PIC24FV16KM204 FAMILY 28-Lead SPDIP (.300") Example PIC24F16KM202 -I/SP e3 1342M7W XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (5.30 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead SOIC (7.
PIC24FV16KM204 FAMILY 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX X XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24FV16KM 204-I/ML e3 1342M7W 48-Lead UQFN (6x6x0.5 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 28.2 Package Details The following sections give the technical details of the packages.
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PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30003030B-page 302 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30003030B-page 304 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
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PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30003030B-page 310 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30003030B-page 312 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
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PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY DS30003030B-page 318 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY DS30003030B-page 320 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30003030B-page 322 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 324 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2013) Original data sheet for the PIC24FV16KM204 family of devices. Revision B (July 2013) Updates all references to PGCx and PGDx pin functions throughout the document to PGECx and PGEDx. Updates Section 4.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 326 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY INDEX A A/D Buffer Data Formats ................................................. 225 Control Registers ..................................................... 212 AD1CHITH/L .................................................... 212 AD1CHS .......................................................... 212 AD1CON1 ........................................................ 212 AD1CON2 ........................................................ 212 AD1CON3 ............................................
PIC24FV16KM204 FAMILY Comparator Voltage Reference ....................................... 239 Configuring ............................................................... 239 Configurable Logic Cell (CLC) ......................................... 195 Configuration Bits ............................................................. 249 CPU ALU ............................................................................ 39 Control Registers .......................................................
PIC24FV16KM204 FAMILY M Master Synchronous Serial Port (MSSP) ......................... 159 Microchip Internet Web Site ............................................. 332 MPLAB Assembler, Linker, Librarian ............................... 262 MPLAB ICD 3 In-Circuit Debugger .................................. 263 MPLAB PM3 Device Programmer ................................... 263 MPLAB REAL ICE In-Circuit Emulator System ................ 263 MPLAB X Integrated Development Environment Software .................
PIC24FV16KM204 FAMILY CMSTAT (Comparator Status) ................................. 238 CMxCON (Comparator x Control) ............................ 237 CORCON (CPU Control) ........................................... 39 CORCON (CPU Core Control) ................................... 90 CTMUCON1H (CTMU Control 1 High) .................... 246 CTMUCON1L (CTMU Control 1 Low) ...................... 244 CTMUCON2L (CTMU Control 2 Low) ...................... 248 CVRCON (Comparator Voltage Reference Control) ..........
PIC24FV16KM204 FAMILY T U Timer1 .............................................................................. 141 Timing Diagrams A/D Conversion ........................................................ 295 Brown-out Reset Characteristics ............................. 284 Capture/Compare/PWM (MCCPx, SCCPx) ............. 285 CLKO and I/O Timing ............................................... 282 Example SPI Master Mode (CKE = 0) ..................... 286 Example SPI Master Mode (CKE = 1) .................
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 332 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 334 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FV 16 KM2 04 T - I / PT - XXX Examples: a) PIC24FV16KM204-I/ML: Wide Voltage Range, General Purpose, 16-Kbyte Program Memory, 44-Pin, Industrial Temp., QFN Package b) PIC24F08KM102-I/SS: Standard Voltage Range, General Purpose with Reduced Feature Set, 8-Kbyte Program Memory, 28-Pin, Industrial Temp.
PIC24FV16KM204 FAMILY NOTES: DS30003030B-page 336 2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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