Datasheet

PIC24F16KL402 FAMILY
DS31037B-page 254  2011 Microchip Technology Inc.
T
Timer1...............................................................................117
Timer2...............................................................................119
Timer3...............................................................................121
Oscillator ................................................................... 121
Overflow Interrupt ..................................................... 121
Timer4...............................................................................125
PR4 Register............................................................. 125
TMR4 Register..........................................................125
TMR4 to PR4 Match Interrupt ...................................125
Timing Diagrams
Capture/Compare/PWM (ECCP1, ECCP2) .............. 215
CLKO and I/O Timing................................................ 213
Example SPI Master Mode (CKE = 0) ...................... 216
Example SPI Master Mode (CKE = 1) ...................... 217
Example SPI Slave Mode (CKE = 0) ........................ 218
Example SPI Slave Mode (CKE = 1) ........................ 219
External Clock........................................................... 211
I
2
C Bus Data............................................................. 220
I
2
C Bus Start/Stop Bits..............................................220
MSSP I
2
C Bus Data.................................................. 222
MSSP I
2
C Bus Start/Stop Bits ..................................222
Timing Requirements
Capture/Compare/PWM (ECCP1, ECCP2) .............. 215
CLKO and I/O ........................................................... 213
Comparator ............................................................... 214
Comparator Voltage Reference Settling Time .......... 214
External Clock........................................................... 211
I
2
C Bus Data (Slave Mode)....................................... 221
I
2
C Bus Data Requirements (Master Mode) ............. 223
I
2
C Bus Start/Stop Bits (Master Mode) ..................... 222
I
2
C Bus Start/Stop Bits (Slave Mode) ....................... 220
PLL Clock Specifications ..........................................212
SPI Mode (Master Mode, CKE = 0) .......................... 216
SPI Mode (Master Mode, CKE = 1) .......................... 217
SPI Slave Mode (CKE = 1) ....................................... 219
Timing Requirements SPI Mode
(Slave Mode, CKE = 0) ............................................. 218
U
UART ................................................................................ 151
Baud Rate Generator (BRG) .................................... 152
Break and Sync Transmit Sequence ........................ 153
IrDA Support............................................................. 153
Operation of UxCTS
and UxRTS Control Pins ......... 153
Receiving in 8-Bit or 9-Bit Data Mode....................... 153
Transmitting in 8-Bit Data Mode ............................... 153
Transmitting in 9-Bit Data Mode ............................... 153
W
Watchdog Timer (WDT) .................................................... 186
Windowed Operation ................................................ 186
WWW Address ................................................................. 257
WWW, On-Line Support ....................................................... 9