Datasheet

 2011 Microchip Technology Inc. DS31037B-page 13
PIC24F16KL402 FAMILY
FIGURE 1-1: PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
PORTA
(1)
RA<0:7>
PORTB
(1)
RB<0:15>
Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-4 and Table 1-5 for
I/O port pin descriptions.
ComparatorsTimer4
Timer3
CCP2
A/D
10-Bit
CCP3
(1) MSSP
CN1-23
(1)
UART
Data EEPROM
OSCI/CLKI
OSCO/CLKO
V
DD,
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR
FRC/LPRC
Oscillators
Timer2Timer1
CCP1/
HLVD
Precision
Reference
Band Gap
ECCP1
(1)
ULPWU
V
SS
ULPWU
1/2
(1)
1/2
(1)