Datasheet

 2011 Microchip Technology Inc. DS31037B-page 129
PIC24F16KL402 FAMILY
REGISTER 16-2: CCP1CON: ECCP1 CONTROL REGISTER (ECCP MODULES ONLY)
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PM1 PM0 DC1B1 DC1B0 CCP1M3
(2)
CCP1M2
(2)
CCP1M1
(2)
CCP1M0
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-6 PM<1:0>: Enhanced PWM Output Configuration bits
If CCP
1M<3:2> = 00, 01, 10:
xx = P1A is assigned as capture input or compare output; P1B, P1C and P1D are assigned as port pins
If CCP
1M<3:2> = 11:
11 = Full-bridge output reverse: P1B is modulated; P1C is active; P1A and P1D are inactive
10 = Half-bridge output: P1A, P1B are modulated with dead-band control; P1C and P1D are
assigned as port pins
01 = Full-bridge output forward: P1D is modulated; P1A is active; P1B, P1C are inactive
00 = Single output: P1A, P1B, P1C and P1D are controlled by steering
bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP1 Module
Capture and
Compare modes:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DC1B<9:2>) of the duty cycle are found in CCPR1L.
bit 3-0 CCP1M<3:0>: CCP1 Module Mode Select bits
(2)
1111 = PWM mode: PA and PC are active-low; PB and PD are active-low
1110 = PWM mode: PA and PC are active-low; PB and PD are active-high
1101 = PWM mode: PA and PC are active-high; PB and PD are active-low
1100 = PWM mode: PA and PC are active-high; PB and PD are active-high
1011 = Compare mode: Special Event Trigger; reset timer on CCP1 match
(CCPxIF bit is set)
1010 = Compare mode: Generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin
reflects I/O state)
1001 = Compare mode: Initialize CCP1 pin high; on compare match, force CCP1 pin low (CCP1IF bit is
set)
1000 = Compare mode: Initialize CCP1 pin low; on compare match, force CCP1 pin high (CCP1IF
bit is set)
0111 = Capture mode: Every 16th rising edge
0110 = Capture mode: Every 4th rising edge
0101 = Capture mode: Every rising edge
0100 = Capture mode: Every falling edge
0011 = Reserved
0010 = Compare mode: Toggle output on match (CCP1IF bit is set)
0001 = Reserved
0000 = Capture/Compare/PWM is disabled (resets CCP1 module)
Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. For all other devices, CCP1CON is
configured as Register 16-1.
2: CCP1M<3:0> = 1011 will only reset timer and not start A/D conversion on CCP1 match.