Datasheet

PIC24F16KL402 FAMILY
DS31037B-page 126  2011 Microchip Technology Inc.
FIGURE 16-1: GENERIC CAPTURE MODE BLOCK DIAGRAM
FIGURE 16-2: GENERIC COMPARE MODE BLOCK DIAGRAM
FIGURE 16-3: SIMPLIFIED PWM BLOCK DIAGRAM
CCPRxH CCPRxL
Set CCPxIF
Q1:Q4
CCPxCON<3:0>
(E)CCPx Pin
Prescaler
 1, 4, 16
and
Edge Detect
TMR3H TMR3L
4
4
CCPRxH CCPRxL
TMR3H TMR3L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCPxIF
CCPx Pin
CCP
CCPxCON<3:0>
Output Enable
Compare
4
(Timer3 Reset)
Match
CCPRxL
CCPRxH (Slave)
Comparator
TMR2
(2)
Comparator
PR2
(2)
(1)
R
Q
S
Duty Cycle Registers
CCPxCON<5:4>
Clear Timer,
CCP1 Pin and
Latch D.C.
CCP
CCPx
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
2: Either Timer2 or Timer4 may be used as the PWM time base.
Output Enable