Datasheet

 2012 Microchip Technology Inc. DS30575A-page 95
PIC18F97J94 FAMILY
5.9 Device Reset Timers
PIC18F97J94 family devices incorporate three sepa-
rate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.9.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F97J94 fam-
ily devices is a counter which uses the INTOSC source
as the clock input. While the PWRT is counting, the
device is held in Reset. The power-up time delay
depends on the INTOSC clock and varies slightly from
chip-to-chip due to temperature and process variation.
See the T
PWRT specification for details. The PWRT is
always enabled and active after Brown-out and
Power-on Reset events.
5.9.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for LP, MS, HS and
HSPLL modes, and only on Power-on Reset or on exit
from most power-managed modes.
5.9.3 PLL LOCK TIME-OUT
The PLL is enabled by programming FOSC<2:0> = 011
(CONFIG2L<2:0>. With the PLL enabled, the time-out
sequence, following a Power-on Reset, is slightly differ-
ent from other oscillator modes. A separate timer is used
to provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (T
RC) follows the oscillator start-up time-out.
5.9.4 RESET STATE OF REGISTERS
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCONx registers are set or
cleared differently in different Reset situations, as
indicated in Tabl e 5 - 2 . These bits are used in software
to determine the nature of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.