Datasheet

PIC18F97J94 FAMILY
DS30575A-page 92  2012 Microchip Technology Inc.
5.2.1.1 Using the POR Circuit
To take advantage of the POR circuit, tie the MCLR pin
directly to V
DD. This will eliminate external RC compo-
nents usually needed to create a POR delay. A
minimum rise time for VDD is required. Refer to the
“Electrical Characteristics” section of the specific
device data sheet for more information.
Depending on the application, a resistor may be
required between the MCLR
pin and VDD. This resistor
can be used to decouple the MCLR
pin from a noisy
power supply rail.
Figure 5-3 displays a possible POR circuit for a slow
power supply ramp up. The external POR circuit is only
required if the device would exit Reset before the
device V
DD is in the valid operating range. The diode,
D, helps discharge the capacitor quickly when V
DD
powers down.
FIGURE 5-3: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER -UP)
5.2.2 V
BAT POWER-ON-RESET (VBPOR)
The device will remain in VBAT mode as long as no
power is present on V
DD. The VBPOR is active when
the device is operating in V
BAT mode and deriving
power from the V
BAT pin. Similar to the POR, the circuit
monitors V
BAT voltage and holds the device in Reset
until adequate voltage is present to power up the
device. After exiting the VBAT POR condition, the
VBPOR (RCON3<1>) bit is set. All other registers will
be in a POR state, including Deep Sleep semaphores.
Minimum V
BAT ramp time and rearm voltage require-
ments apply. Refer to Parameters D003 and D004 in
Section 31.0 “Electrical Characteristics” for details.
The device does not execute code in V
BAT mode. Also,
there is no Power-up Timer associated with VBPOR.
After VDD power is restored, the device exits VBAT
mode and the VBAT (RCON3<0>) bit is set. All other
registers, except those associated with RTCC, its clock
source and the Deep Sleep semaphores (DSGPRx),
will be in a POR state. For more information about V
BAT
mode, see Section 4.5 “Vbat Mode”.
5.3 Master Clear Reset (MCLR)
Whenever the MCLR pin is driven low, the device asyn-
chronously asserts SYSRST
, provided the input pulse
on MCLR
is longer than a certain minimum width, TMCL
(see Section 31.0 “Electrical Characteristics”).
When the MCLR pin is released, SYSRST is also
released. The Reset vector fetch starts from the
SYSRST
release. The processor continues to use the
existing clock source that was in use before the MCLR
Reset occurred. The EXTR status bit (RCON2<7>) is
set to indicate the MCLR
Reset.
5.4 Watchdog Timer Reset (WDT)
Whenever a Watchdog Timer time-out occurs, the
device asynchronously asserts SYSRST
. The clock
source remains unchanged. Note that a WDT time-out
during Sleep or Idle mode will wake-up the processor,
but NOT reset the processor. The TO
bit (RCON<3>) is
cleared when a WDT time-out occurs. Software must
set this bit to initialize the flag. For more information,
refer to Section 28.2 “Watchdog Timer (WDT)”.
Note 1: External Power-on Reset circuit is required
only if the V
DD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when V
DD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1  1 k will limit any current flowing into
MCLR
from external capacitor, C, in the event
of MCLR
/VPP pin breakdown, due to Electro-
static Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
V
DD
MCLR
PIC18FXXJXX
VDD
Note: The WDT described here is not the same
one used in Deep Sleep mode. For more
information on Deep Sleep WDT, see
Section 28.2 “Watchdog Timer (WDT)”.