Datasheet

 2012 Microchip Technology Inc. DS30575A-page 91
PIC18F97J94 FAMILY
FIGURE 5-2: POR MODULE TIMING SEQUENCE FOR RISING VDD
TCSD
VDD
VPOR
POR Circuit Threshold Voltage
SYSRST
TPWRT
Internal Power-on Reset Pulse Occurs
and Begins POR Delay Time, T
CSD
POR Circuit is Initialized at VPOR
Time
System Clock is Started
After T
PWRT Delay
Expires
System Clock is Released
and Code Execution
Begins
POR
PWRT
Note 1: Timer and interval are determined by the initial start-up oscillator configuration; TOSC is for external
oscillator modes, T
FRC is for the FRC Oscillator or TLPRC for the internal 31 kHz RC Oscillator.
(Note 1)
INTERNAL RESET
System Reset is Released
After Clock is Stable
Oscillator Delay
and Code Execution