Datasheet

 2012 Microchip Technology Inc. DS30575A-page 89

PIC18F97J94 FAMILY

U-0 U-0 U-0 R/W-0 U-0 R/C-0 U-0 R/W-0

— — — SRETEN

(1)

— DPSLP

(2)

—PMSLP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 SRETEN: Retention Regulator Voltage Sleep Disable bit

(1)

1 = If RETEN (CONFIG7L<0>) = 0 and the regulator is enabled, the device goes into Retention mode

in Sleep

0 = The regulator is on when device’s Sleep mode is enabled and the Low-Power mode is controlled

by the PMSLP bit

bit 3 Unimplemented: Read as ‘0’

bit 2 DPSLP: Deep Sleep Wake-up Status bit (used in conjunction with the POR

and BOR bits in RCON to

determine the Reset source)

(2)

1 = The last exit from Reset was caused by a normal wake-up from Deep Sleep

0 = The last exit from Reset was not due to a wake-up from Deep Sleep

bit 1 Unimplemented: Read as ‘0’

bit 0 PMSLP: Program Memory Power During Sleep bit

1 = Program memory bias voltage remains powered during Sleep

0 = Program memory bias voltage is powered down during Sleep

Note 1: This bit is available only when RETEN

(CONFIG7L<0>) = 0.

2: This bit is set in hardware only; it can only be cleared in software.