Datasheet

 2012 Microchip Technology Inc. DS30575A-page 87
PIC18F97J94 FAMILY
REGISTER 5-2: RCON2: RESET CONTROL REGISTER 2
R/W-0, HS U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
EXTR
(1)
—SWDTEN
(2)
— — — — —
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EXTR: External Reset (MCLR
) Pin bit
(1)
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 Unimplemented: Read as ‘0’
bit 5 SWDTEN: Software Controlled Watchdog Timer Enable bit
(2)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
bit 4-0 Unimplemented: Read as ‘0’
Note 1: This bit is set in hardware; it can be cleared in software.
2: This bit has no effect unless the Configuration bits, WDTEN<1:0> = 10.