Datasheet

 2012 Microchip Technology Inc. DS30575A-page 85
PIC18F97J94 FAMILY
5.0 RESET
The PIC18F97J94 family devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR
Reset
c) Watchdog Timer (WDT) Reset
d) Configuration Mismatch (CM)
e) Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Underflow/Overflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. For information on WDT Resets, see
Section 28.2 “Watchdog Timer (WDT)”. For Stack
Reset events, see Section 6.1.4.4 “Stack Full and
Underflow Resets”. For Deep Sleep mode, see
Section 4.4 “Deep Sleep Modes”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.1 RCON Registers
Device Reset events are tracked through the RCON,
RCON2, RCON3 and RCON4 registers (Register 5-1,
Register 5-2, Register 5-3 and Register 5-4). The regis-
ter bits indicate that a specific Reset event has occurred.
Depending on the definition, status bits may be set or
cleared by the event, and re-initialized by the applica-
tion, after the event to the opposite state. Setting or
clearing Reset status bits does not cause a Reset.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 10.0 “Interrupts”.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
V
DD Rise
Detect
OST/PWRT
INTOSC
(1)
POR Pulse
OST
10-Bit Ripple Counter
PWRT
Internal Reset
11-Bit Ripple Counter
Enable OST
(2)
Enable PWRT
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC Oscillator of the CLKI pin.
2: See Table 5-1 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
Idle
1024 Cycles
1 ms
32 s
MCLRE
WDT
Time-out
S
R
Q