Datasheet

 2012 Microchip Technology Inc. DS30575A-page 79
PIC18F97J94 FAMILY
4.7 Selective Peripheral Power
Control
Sleep and Idle modes allow users to substantially reduce
power consumption by slowing or stopping the CPU
clock. Even so, peripheral modules still remain clocked,
and thus, consume some amount of power. There may
be cases where the application needs what these modes
do not provide: the ability to allocate limited power
resources to the CPU while eliminating power consump-
tion from the peripherals. The PIC18F97J94 family
addresses this requirement by allowing peripheral
modules to be selectively enabled or disabled, reducing
or eliminating their power consumption.
4.7.1 DISABLING PERIPHERAL
MODULES
Most of the peripheral modules in the PIC18F97J94
family
architecture can be selectively disabled, reduc-
ing, or essentially eliminating, their power consumption
during all operating modes. Two different options are
available to users, each with a slightly different effect.
4.7.2 MODULE ENABLE BIT (XXXEN)
Many peripheral modules have a Module Enable bit,
generically named, “XXXEN”, usually located in Bit
Position 7 of their control registers (or Primary Control
registers for more complex modules). Here, “XXX”
represents the mnemonic form for the module of the
module name. For example, the enable bit for an
MSSPx module is “SSPEN”, and so on. The bit is pro-
vided for all serial and parallel communication modules
and the Real-Time Clock (RTC). Clearing this bit
disables the module’s operation; however, it continues
to receive clock signals and draw a minimal amount of
current.
As with all earlier PIC
®
MCU devices, timers continue to
be under selective operation and are controlled by their
own TON bit, also located in Position 7. The A/D Con-
verter also has a legacy enable bit, ADON, that has the
same function as the XXXEN bits. I/O ports and features
associated with them, such as input change notification
and input capture, do not have their own module enable
bits, since their operation is secondary to other modules.
Disabling modules not required for a particular applica-
tion, in this manner, allows for the selective and
dynamic adjusting power consumption, under software
control, as the application is running.
4.7.3 PERIPHERAL MODULE DISABLE
BIT (XXMD)
All peripheral modules (except for I/O ports) also have
a second control bit that can disable their functionality.
These bits, known as the Peripheral Module Disable
(PMD) bits, are generically named, “XXMD” (using “XX”
as the mnemonic version of the module’s name), as
shown in Section 4.7.2 “Module Enable Bit
(XXXEN)”). These bits are located in the PMDx SFRs.
In contrast to the module enable bits, the XXMD bit
must be set (= 1) to disable the module.
While the PMD and module enable bits both disable a
peripheral’s functionality, the PMD bit completely shuts
down the peripheral, effectively powering down all
circuits and removing all clock sources. This has the
additional effect of making any of the module’s control
and buffer registers, mapped in the SFR space,
unavailable for operations. In other words, when the
PMD bit is used to disable a module, the peripheral
ceases to exist until the PMD bit is cleared. This differs
from using the module enable bit, which allows the
peripheral to be reconfigured and buffer registers
preloaded, even when the peripheral’s operations are
disabled.
The PMD bit is most useful in highly power-sensitive
applications, where even tiny savings in power
consumption can determine the ability of an application
to function. In these cases, the bits can be set before
the main body of the application to remove those
peripherals that will not be needed at all.