Datasheet

PIC18F97J94 FAMILY
DS30575A-page 76  2012 Microchip Technology Inc.
4.5.1 WAKE-UP FROM VBAT MODES
When VDD is restored to a device in VBAT mode, it auto-
matically wakes. Wake-up occurs with a POR, after
which the device starts executing code from the Reset
vector. All SFRs, except the Deep Sleep semaphores
and RTCC registers are reset to their POR values. If
the RTCC was not configured to run during V
BAT mode,
it will remain disabled and RTCC will not run. Wake-up
timing is similar to that for a normal POR.
Wake-up from V
BAT mode is identified by checking the
state of the VBAT bit (RCON3<0>). If this bit is set
when the device is awake and starting to execute the
code from the Reset vector, it indicates that the exit
was from V
BAT mode. To identify future VBAT wake-up
events, the bit must be cleared in software.
When a POR event occurs with no battery connected
to the V
BAT pin, the VBPOR bit (RCON3<1>) becomes
set. On the device, if there is no battery connected to
the VBAT pin, VBPOR will indicate that the battery needs
to be connected to the V
BAT pin.
In addition, if the V
BAT power source falls below the
level needed for Deep Sleep semaphore operation
while in VBAT mode (e.g., the battery has been
drained), the VBPOR bit will be set. VBPOR is also set
when the microcontroller is powered up the very first
time, even if power is supplied to V
BAT.
4.6 Saving Context Data with the
DSGPRx Registers
As exiting VBAT causes a POR, most Special Function
Registers reset to their default POR values. In addition,
because the core power is not supplied in VBAT mode,
information in data RAM will be lost when exiting this
mode. Applications which require critical data to be
saved, should be saved in DSGPR0, DSGPR1,
DSGPR2 and DSGPR3.
Any data stored to the DSGPRx registers must be
written twice. The write operations do not need to be
sequential. However, back-to-back writes are a
recommended programming practice.
After exiting V
BAT mode, software can restore the data
by reading the registers.
4.6.1 I/O PINS DURING VBAT MODE
All I/O pins should be maintained at VSS level; no I/O
pins should be given V
DD (refer to “Absolute
Maximum Ratings
(†)
” in Section 31.0 “Electrical
Characteristics”) during V
BAT mode. The only
exceptions are the SOSCI and SOSCO pins, which
maintain their states if the Secondary Oscillator is
being used as the RTCC clock source. It is the user’s
responsibility to restore the I/O pins to their proper
states, using the TRIS and LAT bits, once V
DD has
been restored.