Datasheet

PIC18F97J94 FAMILY
DS30575A-page 74  2012 Microchip Technology Inc.
TABLE 4-7: DELAY TIMES FOR EXITING RETENTION DEEP SLEEP MODE
Clock Source Exit Delay Oscillator Delay Notes
EC TRETR + TPM — 1, 2, 6
ECPLL TRETR + TPM TLOCK 1, 2, 4, 6
MS, HS TRETR + TPM TOST 1, 2, 3, 6
MSPLL, HSPLL T
RETR + TPM TOST + TLOCK 1, 2, 3, 4, 6
SOSC Off during Sleep TRETR + TPM TOST 1, 2, 3, 6
On during Sleep TRETR + TPM — 1, 2, 6
FRC, FRCDIV T
RETR + TPM TFRC 1, 2, 5, 6
LPRC: Off during Sleep TRETR + TPM TLPRC 1, 2, 5, 6
On during Sleep TRETR + TPM — 1, 2, 6
FRCPLL T
RETR + TPM TLOCK 1, 2, 3, 6
Note 1: TPM = Start-up delay for program memory stabilization; applicable only when IPEN (RCON<7>) = 0.
2: TRETR = Retention regulator start-up delay.
3: T
OST = Oscillator Start-up Timer (OST); a delay of 1024 oscillator periods before the oscillator clock is
released to the system.
4: T
LOCK = PLL lock time.
5: TFRC and TLPRC = RC Oscillator start-up times.
6: TFLASH = Flash program memory ready delay. Setting the PMSLP bit will provide a faster wake-up.