Datasheet

 2012 Microchip Technology Inc. DS30575A-page 73
PIC18F97J94 FAMILY
4.4.10 CONTROL BIT SUMMARY FOR
SLEEP MODES
Table 4-5 shows the settings for the bits relevant to
Deep Sleep modes.
TABLE 4-5: BIT SETTINGS FOR ALL DEEP SLEEP MODES
4.4.11 WAKE-UP DELAYS
The Reset delays associated with wake-up from Deep
Sleep and Retention Deep Sleep modes, in different
oscillator modes, are provided in Table 4-6 and
Table 4-7, respectively.
TABLE 4-6: DELAY TIMES FOR EXITING FROM DEEP SLEEP MODE
Instruction-Based
Mode
DSEN
(DSCONH<7>)
Retention Regulator
DSWDTEN
(CONFIG8H<0>)
RETEN
(CONFIG7L<0>)
SRETEN
(RCON4<4>)
State
Retention Deep Sleep 10 1Enabled 0
Deep Sleep 11 xDisabled x
Note: The PMSLP bit (RCON4<0>) allows the
voltage regulator to be maintained during
Sleep modes.
Clock Source Exit Delay Oscillator Delay Notes
EC T
DSWU —
ECPLL T
DSWU TLOCK 1, 3
MS, HS TDSWU TOST 1, 2
MSPLL, HSPLL TDSWU TOST + TLOCK 1, 2, 3
SOSC (Off during Sleep) T
DSWU TOST 1, 2
(On during Sleep) TDSWU — 1
FRC, FRCDIV TDSWU TFRC 1, 4
LPRC (Off during Sleep) T
DSWU TLPRC 1, 4
(On during Sleep) TDSWU — 1
FRCPLL TDSWU TFRC + TLOCK 1, 3, 4
Note 1: T
DSWU = Deep Sleep wake-up delay.
2: T
OST = Oscillator Start-up Timer; a delay of 1024 oscillator periods before the oscillator clock is released to
the system.
3: T
LOCK = PLL lock time.
4: TFRC and TLPRC are RC Oscillator start-up times.